Chief Verification Strategist

4 days ago

nashik, India beBeeVerification Full time

Sr Design Verification ManagerAt Eximietas Hiring, we seek a Senior Design Verification Lead. This position requires 8+ years of hands-on experience in SoC design verification. Key skills include expertise in verifying high-speed SoCs and protocols such as I2C/I3C, SPI, UART, GPIO, QSPI, PCIe, Ethernet, CXL, MIPI, DDR, and HBM.This role involves leading complex projects, developing comprehensive verification strategies, conducting gate-level simulations and power-aware verification using tools like Xprop and UPF, and collaborating with cross-functional teams to ensure seamless integration of verification efforts.Key Responsibilities:Develop and implement comprehensive verification strategies for both high-speed and low-speed peripherals and high-speed protocols.Conduct gate-level simulations and power-aware verification using Xprop and UPF.Closely collaborate with architects, designers, and pre/post-silicon verification teams to ensure alignment and smooth integration of verification efforts.Analyze and implement System Verilog assertions and functional coverage to ensure thorough verification of design functionality.Provide mentorship and technical guidance to junior verification engineers to enhance team performance.Lead and manage dynamic teams of verification engineers to foster a collaborative work environment.Ensure that all verification signoff criteria are met with clear documentation.Demonstrate strong dedication, work ethic, and commitment to meeting project goals and deadlines.Implement quality standards and best test practices to contribute to continuous improvements in verification methodologies.Work with Synopsys and Cadence verification tools including VCS and Xsim.Integrate third-party VIPs from Synopsys and Cadence to enhance verification coverage.Qualifications:8+ years of hands-on experience in SoC design verification.Expertise in verifying high-speed SoCs and various protocols including I2C/I3C, SPI, UART, GPIO, QSPI, PCIe, Ethernet, CXL, MIPI, DDR, and HBM.Proficiency in System Verilog for verification including assertions and coverage.Experience with gate-level simulations and power-aware verification using Xprop and UPF.Strong hands-on experience with VCS and Xsim from Synopsys and Cadence.Mentorship experience providing guidance to junior engineers and managing verification teams.Able to work effectively with cross-functional teams ensuring collaboration and verification signoff.Strong understanding of verification methodologies and ability to contribute to their improvement.

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