Mulya Technologies | Design Verification Engineer – Fabric/On Chip Network Verification
2 weeks ago
Design Verification Engineer – Fabric/On Chip Network Verification
Fortune 100 Organization
Location: Bangalore
Introduction
We work is more than a job - it's a calling: To build. To design. To code. To consult. To think along with clients and sell. To make markets. To invent. To collaborate. Not just to do something better, but to attempt things you've never thought possible. Are you ready to lead in this new era of technology and solve some of the world's most challenging problems? If so, lets talk.
Your Role and Responsibilities
- As a Functional verification engineer, you will be working on the latest generation of high end, state-of-the-art micro-processors used in servers.
- Lead the development of the verification plans, environment, testbenches and writing testcases for the Cache Coherency Transport Interconnect Fabric in Server Processors.
- Develop skills in Functional verification tools and methodologies.
- Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design
- Work with development team to ensure coverage criteria is met.
Required Technical and Professional Expertise
- 9+ years of experience in Functional Verification of processors or ASICs.
- 3+ years of experience in the following areas
- Computer architecture knowledge.
- Multi-processor Cache Coherency Transport/Network on Chip/Memory Hierarchy verification.
- AXI/AHB/ACE/ACE-lite/CHI/On Chip System Fabric interface verification or any other Processor/SoC coherency transport interconnect fabric verification.
- Knowledge of performance parameters of On Chip Coherency Transport Network designs and ways to stress verify them
- Minimum one full life cycle leadership experience of a processor/SoC verification flow with focus on Coherency Transport Interconnect and/or Network on Chip Verification
- Good object-oriented programming skills in C++/SystermVerilog, scripting languages like Python/Perl.
- Verification knowledge in Clock domain crossing and reset domain crossing
- Knowledge of functional verification methodology like UVM/OVM
- Knowledge of HDLs (VHDL/Verilog)
- Developed test plans and test strategies for IP/unit/block level verification of Coherency Transport Interconnects
- Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow
- Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails
- Experience in driving verification coverage closure including performance testing, stress testing and ability to identify corner case scenarios.
Contact:
Sumit
Mulya Technologies
sumit@mulyatech.com
"Mining The Knowledge Community"
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