Senior High-Speed Analog Chip Developer

6 days ago

thane, India beBeeHighSpeedAnalogLayout Full time

Senior Analog Layout EngineerWe are seeking a seasoned Senior Analog Layout Engineer to spearhead high-speed analog chip development in cutting-edge TSMC 5nm technology.The ideal candidate will be an individual contributor, accountable for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision.This role demands deep technical expertise in chip-level integration, bump planning, and ESD implementation, along with a comprehensive understanding of circuit simulation concepts.The engineer will collaborate closely with SoC, Circuit, and Digital teams to ensure robust layout quality and performance.Key Responsibilities:Handle chip-level planning and integration of high-speed analog IPs.Perform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimization.Run post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematic.Lead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checks.Drive complete IP signoff ownership, ensuring zero violations at final GDS delivery.Closely work with foundry teams for PDK clarifications, LVS/DRC rule updates, model issues, and tape-out requirements.Coordinate with PD, DV, circuit design, and packaging teams for smooth IP-level delivery.Prepare and deliver IP documentation, abstracts, verification reports, and GDS.Required Skills and Qualifications:8+ years of solid experience in Analog/Mixed-Signal Layout.Deep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks).Strong understanding of chip-level integration, hierarchy, and physical interfaces.Hands-on experience with ICC2 and top-level integration flows.Ability to run simulations for the blocks being designed (post-layout, extracted).Detailed understanding of IP-level verification, DRC/LVS/ERC, PEX/RC extraction, and signoff decks & reliability checks.Proven experience interacting with foundry teams for rule clarifications and IP/tape-out signoff.Excellent command of Cadence Virtuoso, PVS, Calibre, and extraction tools.Benefits:Experience working on advanced nodes (5nm).Exposure to SERDES / PCIe / MIPI / USB high-speed IPs.Opportunity to work with global customers.],

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