Chief Verification Specialist for Digital Designs

1 week ago


hyderabad, India beBeeSeniorDesignVerificationEngineer Full time

Job OverviewWe are seeking an experienced professional to join our team as a Senior Design Verification Engineer.



  • Hyderabad, India ACL Digital Full time

    SSOC Design Verification Engineer - Senior / Lead / Sr. LeadExperience: 5 to 12 YearsLocation: Hyderabad / BangaloreJob RequirementMust have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC.Experience of working on...


  • Hyderabad, India ACL Digital Full time

    #ACL Digital is Hiring: GPM Subsystem Verification EngineerMust-have: UVM, System Verilog, IP VerificationPreferred: Power Management IP, Firmware DV, Python/PerlFull-cycle DV: test plan → tape outCollaborate with top DV, design & architecture teamsApply/Refer: #ACLDigital #Hiring Now #Design Verification #UVM #System Verilog#Power Management IP #Hyderabad...


  • Hyderabad, India ACL Digital Full time

    #ACL Digital is Hiring: GPM Subsystem Verification EngineerMust-have: UVM, System Verilog, IP VerificationPreferred: Power Management IP, Firmware DV, Python/PerlFull-cycle DV: test plan → tape outCollaborate with top DV, design & architecture teamsApply/Refer: #ACLDigital #Hiring Now #Design Verification #UVM #System Verilog#Power Management IP #Hyderabad...


  • Hyderabad, India ACL Digital Full time

    #ACL Digital is Hiring: GPM Subsystem Verification Engineer Must-have: UVM, System Verilog, IP Verification Preferred: Power Management IP, Firmware DV, Python/Perl Full-cycle DV: test plan → tape out Collaborate with top DV, design & architecture teams Apply/Refer: #ACLDigital #HiringNow #DesignVerification #UVM #SystemVerilog #PowerManagementIP...


  • Hyderabad, India ACL Digital Full time

    #ACL Digital is Hiring: GPM Subsystem Verification Engineer Must-have: UVM, System Verilog, IP Verification Preferred: Power Management IP, Firmware DV, Python/Perl Full-cycle DV: test plan → tape out Collaborate with top DV, design & architecture teams Apply/Refer: #ACLDigital #HiringNow #DesignVerification #UVM #SystemVerilog #PowerManagementIP...


  • Hyderabad, India ACL Digital Full time

    SSOC Design Verification Engineer - Senior / Lead / Sr. LeadExperience: 5 to 12 YearsLocation: Hyderabad / BangaloreJob RequirementMust have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC.Experience of working on...


  • Hyderabad, India ACL Digital Full time

    SSOC Design Verification Engineer - Senior / Lead / Sr. LeadExperience: 5 to 12 YearsLocation: Hyderabad / BangaloreJob Requirement- Must have good knowledge on the verification flows- Excellent hands-on debug skills and problem solving attitude.- Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC.- Experience of working...


  • hyderabad, India ACL Digital Full time

    SSOC Design Verification Engineer - Senior / Lead / Sr. LeadExperience: 5 to 12 YearsLocation: Hyderabad / BangaloreJob Requirement- Must have good knowledge on the verification flows- Excellent hands-on debug skills and problem solving attitude.- Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC.- Experience of working...


  • Hyderabad, India ACL Digital Full time

    SSOC Design Verification Engineer - Senior / Lead / Sr. LeadExperience: 5 to 12 YearsLocation: Hyderabad / BangaloreJob Requirement- Must have good knowledge on the verification flows- Excellent hands-on debug skills and problem solving attitude.- Experience of working in complex test-bench/model in Verilog, System Verilog or System C.- Experience of working...


  • Hyderabad, India ACL Digital Full time

    SSOC Design Verification Engineer - Senior / Lead / Sr. Lead Experience: 5 to 12 Years Location: Hyderabad / Bangalore Job Requirement Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC. Experience of working...