Design Verification Engineer

2 days ago


Hyderabad, India ACL Digital Full time

#ACL Digital is Hiring: GPM Subsystem Verification Engineer Must-have: UVM, System Verilog, IP Verification Preferred: Power Management IP, Firmware DV, Python/Perl Full-cycle DV: test plan → tape out Collaborate with top DV, design & architecture teams Apply/Refer: #ACLDigital #HiringNow #DesignVerification #UVM #SystemVerilog #PowerManagementIP #HyderabadJobs #VLSICareers



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    #ACL Digital is Hiring: GPM Subsystem Verification Engineer Must-have: UVM, System Verilog, IP Verification Preferred: Power Management IP, Firmware DV, Python/Perl Full-cycle DV: test plan → tape out Collaborate with top DV, design & architecture teams Apply/Refer: #ACLDigital #HiringNow #DesignVerification #UVM #SystemVerilog #PowerManagementIP...

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