High-Performance Analog Design Engineer

2 weeks ago

kolkata, India beBeeExpertise Full time

Senior Analog Layout Engineer PositionWe are seeking a highly experienced Senior Analog Layout Engineer with strong expertise in chip-level handling of high-speed analog IPs, deep understanding of ICC2-based top-level integration, and the ability to independently run block-level simulations.This role demands ownership of IP development, verification, integration, and delivery. The candidate will work closely with SoC, Circuit, and Digital teams to ensure robust layout quality and performance.Key Responsibilities:Handle chip-level planning and integration of high-speed analog IPs.Perform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimization.Run post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematic.Lead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checks.Drive complete IP signoff ownership, ensuring zero violations at final GDS delivery.Requirements:8+ years of solid experience in Analog/Mixed-Signal Layout.Deep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks).Strong understanding of chip-level integration, hierarchy, and physical interfaces.Hands-on experience with ICC2 and top-level integration flows.Benefits:Excellent command of Cadence Virtuoso, PVS, Calibre, and extraction tools.Strong ownership of IP delivery, customer communication, and documentation.Good To Have:Experience with advanced nodes (5nm).Exposure to SERDES / PCIe / MIPI / USB high-speed IPs.Experience working with global customers.Location: Remote / India (must support USA/Canada time zone)Travel: Willing to travel to the U.S. for project release (as required)

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