Chief DFT Architect

2 weeks ago

junagadh, India beBeeDft Full time

Key Responsibilities:Define and drive DFT strategy and architecture for multiple projects.Implement and verify DFT features like scan insertion, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan, IJTAG.Manage end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Owning DFT signoff, timing closure, and ATE pattern delivery.Required Skills and Experience:B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.Strong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Benefits:Competitive salary.Leadership exposure and fast-track growth opportunities.Join our team of experts and be part of innovative SoC and ASIC design.

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