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Principal Engineer
2 months ago
Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B) global organization? We offer all that and more at Microchip Technology, Inc.
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our ; we affectionately refer to it as the and it’s won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you.
Visit our page to see what exciting opportunities and company await
Job Description:
The primary objective of this role is to create and use verification environments to verify digital based productsand contribute to the verification methodology development and project execution resulting in new and/orimproved products.
The successful candidate will be responsible for the entire verification flow of the product to be tested, from verification architectureconceptual planto release of the product into silicon and into production.
Main Responsibilities
Define products test plans
Define and implement UVM and SystemVerilog based verification frameworks
Code UVM components, tests andsequences
Define and implement functional coverage
Perform verification of digital and mixed-signal products: run RTL and gate level simulations; analyze and debug simulation results and interact with the design team; run RTL and gate level regressions for product streamout
Support validation of silicon
Requirements/Qualifications:
Mandatory Skills
Proficiency in System Verilog
Proficiency in UVM methodology
Extensive experience in building digital verification frameworks from scratch, using UVM
methodology
Proficiency in System Verilog Assertions
Must be able and willing to investigatein detailthe designed productand develop a tailored and comprehensive verification bench
Must have good problem-solving skills
Must have good communication skills and ability to work effectively in a team
Must be self-motivated to produce best quality results
Preferred Skills
Knowledge of scripting languages (Python, Perl, Tcl, …)
Experience with NVM memory products, highly preferable
Experience with mixed signal products
Education
Bachelor’s degree or higher
Experience
Minimum 8 years’ experience in UVM verification
Travel Time:
0% - 25%