Senior Block-Level Physical Design Engineer

About the RoleWe are seeking an experienced Senior Analog Layout Engineer to work on high-speed analog chip development in advanced technology. The ideal candidate will be responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision.Key ResponsibilitiesHandle chip-level planning and integration of high-speed...

IO Design Engineer (GPIO / I2C / I3C Experience Required) Role & ResponsibilitiesDesign and development of IO circuits for advanced semiconductor nodes.Develop GPIO, I2C, and I3C IP blocks meeting performance, area, and power targets.Work closely with analog, digital, and physical design teams to ensure seamless integration.Perform simulations, verification,...

Senior Analog Layout EngineerWe are seeking a seasoned Senior Analog Layout / IP Delivery Engineer with profound expertise in designing and integrating high-speed analog IPs at the chip level.This role demands extensive knowledge of ICC2-based top-level integration, thorough IP verification experience, and the ability to run block-level simulations...

Senior Analog Circuit Design EngineerWe are seeking a highly skilled and experienced Senior Analog Circuit Design Engineer to join our team.The ideal candidate will have a strong background in CMOS analog design fundamentals, with hands-on experience in designing analog circuit blocks, SERDES-related circuits, and proficiency in Cadence Virtuoso Schematic &...

Job DescriptionDFT engineers are responsible for designing and implementing digital design for testability (DFT) solutions. This involves understanding complex concepts like scan insertion, ATPG, coverage analysis, and transition delay test coverage.They must have hands-on experience in inserting MBIST, validating memory tests, and defining test mode timing...

Job Summary:Full Chip STA LeadWe are seeking an accomplished STA Specialist to spearhead timing closure activities for intricate SoCs.This role will involve handling functional and test constraints at block and top level, performing static timing analysis (STA) for block-level and full-chip sign-off, owning ECO generation at the top level and coordinating...

Hi All,Eximietas Design Hiring Senior SoC Design Verification Architects / Sr. Manager.Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:# Lead SoC Design Verification efforts for complex projects, ensuringsuccessful execution of verification plans.#...

Lead Chip Design SpecialistDrive top-level design activities for complex high-performance SoCs.Manage database integration and updates for derivative chips.Ensure block integration and Physical Verification sign-off.Develop automation and improve flow efficiency using scripting languages.Key Requirements:8+ years of experience in Full Chip Design.Proven...

Job OverviewWe are seeking a seasoned professional to assume the role of Full Chip STA Lead, with expertise in full-chip timing and constraint management.This key position will drive the process of timing closure for complex SoCs, providing technical guidance to junior engineers.Functional and test constraints at block and top level must be effectively...

Senior Interior Designer – Hamerkop Design Studio, BangaloreExperience: 3+ yearsAdded Advantage: Graphic design skills (Illustrator preferred)Responsibilities:    •   Lead interior design projects end-to-end    •   Prepare concepts, drawings, presentations & BOQs    •   Coordinate with clients, vendors & site...