Senior Architect

3 days ago


anand, India beBeeDft Full time

Lead DFT Engineer RoleThis position involves leading the architecture, planning, and implementation of Digital Fault Tolerance across complex System on Chip/ASIC designs. As a key member of our team, you will guide junior engineers, collaborate with cross-functional teams, and ensure exceptional testability and manufacturability of silicon products.Main Responsibilities:Develop and drive Digital Fault Tolerance strategy and architecture for multiple projects.Lead the implementation and verification of Digital Fault Tolerance features such as scan insertion and compression, ATPG pattern generation, and boundary scan.Manage end-to-end Digital Fault Tolerance flow from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.



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