Senior Digital Fault Tolerance Expert

1 week ago

thiruvananthapuram, India beBeeDft Full time

Lead DFT Engineer Job OpportunityWe are seeking a Lead DFT Engineer to spearhead the development of complex SoC/ASIC designs. As a technical leader, you will oversee junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.DFT Strategy and Architecture: Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Implementation and Verification: Spearhead implementation and verification of DFT features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan, and IJTAG.End-to-End DFT Flow Management: Oversee end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.About This RoleDevelop and implement effective DFT strategies that meet project requirements.Oversight of DFT design, testing, and verification processes.Identification of areas for process improvement and development of corrective actions.Mentor and guide junior engineers in DFT best practices and technologies.Development of knowledge sharing resources and training programs.RequirementsBachelor's or Master's degree in Electronics, Electrical, or VLSI Design.Minimum 7 years of experience in DFT for complex ASIC or SoC designs.Strong understanding of scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with leading DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.Desirable QualificationsFamiliarity with hierarchical DFT methodologies and low-power DFT.Experience with post-silicon validation and failure analysis.Knowledge of safety-critical designs (ISO 26262) and functional safety standards.Working experience in advanced nodes (e.g., 7nm, 5nm, FinFET).

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