Wipro | ASIC RTL design
2 days ago
Seeking a skilled RTL Design Lead/Manager (ASIC)
:
- 6-28 years experience in VLSI RTL IP/Subsystem design
- Expertise in SoC Clock, Power IP/Subsystem, BUS/Subsystem, and more
Profound grasp of Digital design principles, especially AMBA SoC BUS protocols like APB, AXI, and AHB.
Crafting micro-architecture and detailed design docs for SoC Subsystem, focusing on performance, power, and area requirements.
Exceptional debugging skills and extensive experience with DV tools like Verdi, NCSIM.
Preferable experience in SOC Integration at Top Level, Block Level, or Subsystem level.
Collaborating with DV team for verification coverage enhancement and GLS closure with DV, PD, and Modeling team.
Knowledge in CDC, Linting, UPF, DFT, and Multi-Voltage-Rule-Check analysis.
Familiarity with ASIC Synthesis, static timing reports analysis, Formal checking, etc.
Defining constraints, ensuring critical high-speed path timing closure with back end teams.
Exposure to quality processes in SoC design and verification is a plus.
Thrive in a fast-paced consumer SoC design environment with stringent deadlines and quality benchmarks.
CV submission: pathan.khan@wipro.com
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ASIC SOC RTL Design
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Bangalore, India Wipro Full timeWipro Hiring Senior ASIC/SoC RTL Lead/Manager with 4-18 Yrs of Experience! ℹ️ About the Role: - Require expertise in SoC subsystem/IP design - Must have in-depth knowledge of RTL quality checks (Lint, CDC)- Good understanding of AMBA bus protocols is essential - Knowledge in interface protocols like PCIe, DDR, Ethernet, and more is a plus - Proficiency...
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1 month ago
bangalore, India Wipro Full timeWipro Hiring Senior ASIC/SoC RTL Lead/Manager with 4-18 Yrs of Experience!ℹ️ About the Role:- Require expertise in SoC subsystem/IP design- Must have in-depth knowledge of RTL quality checks (Lint, CDC)- Good understanding of AMBA bus protocols is essential- Knowledge in interface protocols like PCIe, DDR, Ethernet, and more is a plus- Proficiency in...
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2 months ago
bangalore, India Wipro Full timeWipro Hiring Senior ASIC/SoC RTL Lead/Manager with 4-18 Yrs of Experience! ℹ️ About the Role: - Require expertise in SoC subsystem/IP design - Must have in-depth knowledge of RTL quality checks (Lint, CDC) - Good understanding of AMBA bus protocols is essential - Knowledge in interface protocols like PCIe, DDR, Ethernet, and more is a plus - Proficiency...
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Bangalore City, India Wipro Full timeWipro Hiring Senior ASIC/So C RTL Lead/Manager with 4-18 Yrs of Experience!ℹ️ About the Role:- Require expertise in So C subsystem/IP design- Must have in-depth knowledge of RTL quality checks (Lint, CDC)- Good understanding of AMBA bus protocols is essential- Knowledge in interface protocols like PCIe, DDR, Ethernet, and more is a plus- Proficiency in...
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bangalore, India Wipro Full timeSeeking a skilled RTL Design Lead/Manager (ASIC)🌟𝗝𝗼𝗯 𝗗𝗲𝘀𝗰𝗿𝗶𝗽𝘁𝗶𝗼𝗻:- 6-28 years experience in VLSI RTL IP/Subsystem design- Expertise in SoC Clock, Power IP/Subsystem, BUS/Subsystem, and more𝟏. Profound grasp of Digital design principles, especially AMBA SoC BUS protocols like APB, AXI, and AHB.𝟐. Crafting...
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Senior ASIC RTL SOC Design Lead
2 months ago
Bangalore, India Wipro Full timeAbout the Company: Hi All, Greetings from Wipro...! We are Hiring Senior ASIC/SoC RTL Leads/Managers with ~5-20 years of experience to join our Wipro team! About the Role: Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint,...
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bangalore, India Wipro Full timeAbout the Company:Hi All,Greetings from Wipro...!We are Hiring Senior ASIC/SoC RTL Leads/Managers with ~5-20 years of experience to join our Wipro team!About the Role:Expertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System VerilogIn depth knowledge on RTL quality checks (Lint, CDC)Knowledge...
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bangalore, India Wipro Full timeAbout the Company: Hi All, Greetings from Wipro...! We are Hiring Senior ASIC/SoC RTL Leads/Managers with ~5-20 years of experience to join our Wipro team! About the Role: Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint,...
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Senior Asic Rtl Soc Lead
3 months ago
Bangalore City, India Wipro Full timeAbout the Company:Hi All,Greetings from Wipro...!We are Hiring Senior ASIC/SoC RTL Leads/Managers with ~5-20 years of experience to join our Wipro team!About the Role:Expertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System VerilogIn depth knowledge on RTL quality checks (Lint, CDC)Knowledge...
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Bangalore, India Wipro Full timeSeeking a skilled RTL Design Lead/Manager (ASIC) : - 6-28 years experience in VLSI RTL IP/Subsystem design - Expertise in So C Clock, Power IP/Subsystem, BUS/Subsystem, and more . Profound grasp of Digital design principles, especially AMBA So C BUS protocols like APB, AXI, and AHB. . Crafting micro-architecture and detailed design docs for So C...
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bangalore, India Wipro Full timeAbout the Company:Hi All,Greetings from Wipro...!We are Hiring Senior ASIC/SoC RTL Leads/Managers with ~5-20 years of experience to join our Wipro team!About the Role:Expertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System VerilogIn depth knowledge on RTL quality checks (Lint, CDC)Knowledge...
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1 day ago
Bangalore, India Wipro Full timeSeeking a skilled RTL Design Lead/Manager (ASIC) : - 6-28 years experience in VLSI RTL IP/Subsystem design - Expertise in SoC Clock, Power IP/Subsystem, BUS/Subsystem, and more . Profound grasp of Digital design principles, especially AMBA SoC BUS protocols like APB, AXI, and AHB. . Crafting micro-architecture and detailed design docs for SoC...
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1 month ago
bangalore, India Wipro Full timeSenior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols)Exp 4-15yrsLocation :Bengaluru, Hyderabad, Pune, Noida, Kochi1) Expertise in SoC subsystem/IP design2) Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog3) In depth knowledge on RTL quality checks (Lint, CDC)4)...
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Wipro | ASIC RTL Engineer | bangalore
1 month ago
bangalore, India Wipro Full timeSenior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols) Exp 4-15yrs Location :Bengaluru, Hyderabad, Pune, Noida, Kochi 1) Expertise in SoC subsystem/IP design 2) Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog 3) In depth knowledge on RTL quality checks (Lint,...
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Wipro | ASIC RTL Engineer | bangalore
1 month ago
bangalore, India Wipro Full timeSenior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols) Exp 4-15yrs Location :Bengaluru, Hyderabad, Pune, Noida, Kochi 1) Expertise in SoC subsystem/IP design 2) Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog 3) In depth knowledge on RTL quality checks (Lint,...
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ASIC RTL Engineer
1 month ago
bangalore, India Wipro Full timeSenior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols) Exp 4-15yrs Location :Bengaluru, Hyderabad, Pune, Noida, Kochi 1) Expertise in SoC subsystem/IP design 2) Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog 3) In depth knowledge on RTL quality checks (Lint,...
