Senior DFT Architect

1 week ago

kanpur, India beBeeDigitalFaultTolerance Full time

Job OverviewWe are seeking a highly skilled and experienced Digital Fault Tolerance (DFT) Engineer to lead our DFT architecture, planning, and implementation across complex System-on-Chip (SoC)/Application-Specific Integrated Circuit (ASIC) designs. As a key member of our team, you will be responsible for driving the development of world-class testability and manufacturability of silicon products.Key ResponsibilitiesDevelop and drive DFT strategy and architecture for multiple ASIC/SoC projects.Lead the implementation and verification of DFT features such as scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan, and IJTAG.Manage the end-to-end DFT flow from Register-Transfer Level (RTL) to gate-level netlist and silicon bring-up.Collaborate with RTL, Static Timing Analysis (STA), Physical Design (PD), and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure, and Automatic Test Equipment (ATE) pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.RequirementsBachelor's or Master's degree in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.Strong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred QualificationsMaster's degree in Electronics, Electrical, or VLSI Design.8+ years of experience in DFT for complex ASIC or SoC designs.Ph.D. in Electronics, Electrical, or VLSI Design. 

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