SOC Verification Engineer
3 days ago
Responsibilities :
- Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
- Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) .
- Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue.
- Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
- Adhere to quality standards and good test and verification practices.
Skillsets/Requirements :
- B.E/B. Tech/M.E/M. Tech in electronics with 3+ year experience in verification domain.
- Good understanding of Soc level verification testbench and flows.
- Prior work on NoC/Interconnects end to end DV at SoC level with exposure to Bus protocols, Exclusive, Coherency, Performance, Latency, clock gating etc.
- Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI.
- Solid hands-on working experience on System Verilog and UVM methodology.
- Experience in coding assertions and functional coverage bins.
- Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration.
- Can work with scripting language (shell, Makefile, Perl )
- Strong understanding of design concepts and ASIC flows.
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