IO Layout Engineer

1 day ago

bangalore district, India ACL Digital Full time

Job Title: IO Layout Engineer

Experience: 3+ Years

Location: Bangalore

Employment Type: Full-time

Industry: Semiconductors / ASIC / VLSI / IO & ESD Design

Job Summary:

We are looking for a highly motivated and experienced IO Layout Engineer to join our custom layout team. The candidate will be responsible for full-custom layout of IO cells, ESD protection structures, and high-voltage interfaces for ASIC/SoC applications in deep submicron and FinFET technologies.

Key Responsibilities:

  • Perform transistor-level custom layout of various types of IO cells including:
  • Standard IOs (CMOS, LVTTL, LVCMOS, SSTL, HSTL)
  • High-speed and specialty IOs (DDR, USB, PCIe, HDMI, etc.)
  • ESD structures, pad rings, and protection circuits
  • Work closely with IO circuit designers to interpret schematics and design intent.
  • Ensure robust layout practices for:
  • ESD compliance
  • Latch-up prevention
  • Electromigration (EM)
  • Voltage isolation and guard ring planning
  • Ensure layout meets foundry-specific DRC, LVS, and antenna rules.
  • Run and close physical verification (DRC, LVS, ERC, ANT) using industry-standard tools.
  • Participate in floorplanning of IO ring and integration with analog/digital blocks.
  • Coordinate with packaging, ESD, and reliability teams to support silicon tapeout.

Required Skills and Experience:

  • B.E/B.Tech or M.E/M.Tech in Electronics, Electrical Engineering, or VLSI.
  • 3+ years of hands-on experience in IO and/or ESD layout.
  • Strong understanding of ESD protection concepts and latch-up avoidance.
  • Expertise in Cadence Virtuoso for layout design and implementation.
  • Experience with DRC/LVS tools (Calibre, Assura, PVS).
  • Familiarity with advanced process technologies (28nm, 16nm, 7nm, FinFET, etc.).
  • Good knowledge of layout-dependent effects (LDE), IR drop, and reliability constraints.
  • Attention to detail and strong debugging/problem-solving skills.

Preferred Qualifications:

  • Experience in high-voltage or multi-voltage IO layout (1.8V/3.3V/5V interfaces).
  • Experience with IO ring planning and integration in complex SoC floorplans.
  • Familiarity with power grid design, bump/ball map coordination, and ESD co-design.
  • Scripting experience in SKILL, Tcl, or Python for layout automation.

Interested can share Cv to Sharmila.b@acldigital.com

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