ASIC Physical Design Engineer

3 weeks ago


india Infinera Full time

Infinera is a global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10 Tier 1 service providers and 6 of the top 7 ICPs. We design, develop and deliver hardware and software for fiber-based connectivity solutions that span access, aggregation, metro, long haul, and submarine network. Our industry-leading, trendsetting edge-to-core solutions provide the foundation for many of the world’s largest and most demanding networks that generate billions in service revenue for our customers.


Title: ASIC Physical Design Engineer

Location: India


  • Your Key Responsibilities Would Include:
  • Perform physical implementation steps including floor planning, place and route, power/clock distribution for congestion analysis and timing closure at block level as well as full chip
  • Work with logic designers to drive feasibility studies and explore design trade-off for physical design closure
  • Perform technical evaluations of vendor, process nodes and IP and provide recommendations
  • Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII
  • Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off


  • Education & Experience Necessary For Success:


  • 2+ years of experience in ASIC physical design flow and methodologies in 5/7nm and 16nm process nodes
  • Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
  • Experience with EDA Place & Route tools like ICC2 or Innovus or similar tools and Timing tools like Primetime or similar
  • Scripting experience in TCL, python or perl
  • Candidates must have a Bachelor's Degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics..



  • india Infinera Full time

    Infinera is a global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10 Tier 1 service providers and 6 of the top 7 ICPs. We design, develop and deliver hardware...

  • ASIC/SoC Design

    1 month ago


    india Tekwissen India Full time

    Overview: TekWissen Group is a workforce management provider throughout India and many other countries in the world. The below client represents the connected world, offering innovative and customer-centric information technology experiences Position: ASIC/SoC Design Location: Bangalore Duration: Full Time Job Description: 3...


  • india MosChip® Full time

    He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have...


  • india MosChip® Full time

    He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have...


  • india Mulya Technologies Full time

    ASIC Design DirectorLocation: Bangalore We enable tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage,...


  • India Mulya Technologies Full time

    ASIC Design Director Location: Bangalore We enable tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage,...


  • india Wipro Full time

    Wipro is hiring Physical Design Manager for ODC & Client Projects About Us: Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting,...

  • DFT Engineer

    4 weeks ago


    Anywhere in India/Multiple Locations Amk technologies Full time

    Key Responsibilities :- Develop and implement DFT architectures and methodologies for digital ASIC designs.- Design and integrate scan chains, test points, boundary scan, and built-in self-test (BIST) circuits.- Perform DFT insertion, scan stitching, and ATPG (Automatic Test Pattern Generation).- Conduct fault simulation, test pattern generation, and...

  • ASIC - RTL Design

    3 weeks ago


    india eInfochips (An Arrow Company) Full time

    4-8 yrs of experience in RTL design in Verilog, VHDL FPGA experience Xilinx or Altera/Intel or lattice or Microsemi FPGA tools RTL debug experience Database management between FPGA and ASIC RTL Familiarity with front- end RTL tools (RTL Simulation, Synthesis, DFT, Timing) RTL Design modification/ adaptation for FPGA implementation (memories, IO,...

  • ASIC - RTL Design

    3 weeks ago


    india eInfochips (An Arrow Company) Full time

    4-8 yrs of experience in RTL design in Verilog, VHDL FPGA experience Xilinx or Altera/Intel or lattice or Microsemi FPGA tools RTL debug experience Database management between FPGA and ASIC RTL Familiarity with front- end RTL tools (RTL Simulation, Synthesis, DFT, Timing) RTL Design modification/ adaptation for FPGA implementation (memories, IO,...


  • india 7Rays Semiconductors India Private Limited Full time

    4+ years experience in Physical DesignExperience in Floorplanning for SoC using InnovusMust have a knowledge and implementation strategies to create an IO ring in accordance design specificationHave a deep knowledge on ESD, latch-up etc for foundary requirements and placement strategiesShould have a higherarchial design implementation knowledge which include...


  • India eInfochips (An Arrow Company) Full time

    Role: Senior Engineer – ASIC Design VerificationLocation: Across IndiaExperience: 4 to 8 YearsWORK FROM OFFICE : Bangalore | Hyderabad |Chennai |Noida | Ahmedabad |PuneABOUT eInfochips (An Arrow Company):eInfochips, an Arrow company (A $30B, NASDAQ listed (ARW); Ranked #102 on the Fortune List), is a leading global provider of product engineering and...


  • India eInfochips (An Arrow Company) Full time

    Role: Senior Engineer – ASIC Design Verification Location: Across India Experience: 4 to 8 Years WORK FROM OFFICE : Bangalore | Hyderabad |Chennai |Noida | Ahmedabad |Pune ABOUT eInfochips (An Arrow Company): eInfochips, an Arrow company (A $30B, NASDAQ listed (ARW); Ranked #102 on the Fortune List), is a leading global provider of product engineering...


  • Anywhere in India/Multiple Locations Xenspire Technologies Full time

    Job Title:Physical Design Engineer (PD/VLSI)Job Summary:Xenspire Technologies is seeking a highly skilled Physical Design Engineer to lead the physical implementation of complex integrated circuit (IC) designs from RTL to GDSII. As a key member of our design team, you will collaborate closely with design, architecture, and verification teams to achieve...


  • India Mulya Technologies Full time

    Principal PnR (Place and Route) Engineer Bangalore Principal PnR (Place and Route) Engineer Bangalore Full-Time / We are looking for a Principal experienced place-and-route engineer, who is capable of driving the required digital backend flows to create our designs. The ability to work closely with rtl design team to understand partition architecture and...


  • India Mulya Technologies Full time

    Senior Principal / Principal Physical Design Engineer Bangalore Our main business focuses on automotive microcontrollers and SoCs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips. We will continue to integrate the latest electronic and electrical architecture...

  • Principal Engineer

    1 month ago


    india Mulya Technologies Full time

    A large MNC with Market Cap over 50 Billion USD Principal Engineer, Physical Design (10-15 years experience) Location: Bangalore Would you like to work for an ambitious and dynamic startup company that is rapidly expanding into multiple verticals? Are you interested in developing novel and exclusive technology in a cutting-edge industry? Are you...


  • india Mulya Technologies Full time

    Senior Principal / Principal Physical Design EngineerBangaloreOur main business focuses on automotive microcontrollers and SoCs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips.We will continue to integrate the latest electronic and electrical architecture (E/EA)...


  • India Mulya Technologies Full time

    Senior Principal / Principal DFT Engineer – Bangalore, India Description Our main business focuses on automotive microcontrollers and SoCs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips. we will continue to integrate the latest electronic and electrical...


  • india eInfochips (An Arrow Company) Full time

    Experience in hands on PD for 4 to 15 yrs Proven experience in top level floorplanning/block partitioning, Power planning. Understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff. Engineer should have experience in handling chips of GHz clock frequency range &...