ASIC - RTL Design

2 months ago


india eInfochips (An Arrow Company) Full time
  • 4-8 yrs of experience in RTL design in Verilog, VHDL
  • FPGA experience
  • Xilinx or Altera/Intel or lattice or Microsemi FPGA tools
  • RTL debug experience
  • Database management between FPGA and ASIC RTL
  • Familiarity with front- end RTL tools (RTL Simulation, Synthesis, DFT, Timing)
  • RTL Design modification/ adaptation for FPGA implementation (memories, IO, clocking etc. )
  • Design optimization to achieve FPGA area/ performance goals
  • Work closely with DV and Firmware/ Software teams during the entire validation process; including post- silicon bring- up Responsibilities
  • Be able to work and communicate with multi- site teams
  • Responsible for the review of FPGA netlist releases (block/ chip)


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