Current jobs related to Multiple Open Roles - bangalore district - Capgemini Engineering
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Multiple Open Roles
2 weeks ago
Bangalore, India Capgemini Engineering Full timeCapgemini Weekend Hiring Drive On Below Multiple Roles – 15th November (Saturday)
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Multiple Open Roles
2 weeks ago
bangalore, India Capgemini Engineering Full timeCapgemini Weekend Hiring Drive On Below Multiple Roles – 15th November (Saturday) 🚀We are excited to invite talented professionals to join our team! If you have expertise in Cisco technologies and are looking for your next big opportunity, this is for you.📍 Locations: Pune | Mumbai | Bangalore | Gurgaon🗓 Date: 15th November (Saturday)📩 Send...
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Opening for Senior RTL design role
2 weeks ago
bangalore district, India UST Full timeHi Opening for RTL Design Lead role 4-12+ yrs exp, FEINT (front end integration), skill set on RTL linting, CDC/RDC checks, logic synthesis, LEC in ECO context. Please share your resume to jayalakshmi.r2@ust.com Regards, Jaya
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Opening for FPGA Design role
2 days ago
bangalore, India UST Full timeHi,We have an opening for FPGA Design engineer role - BangaloreREQUIRED: EXP: 5 to 12 years Experience with FPGA system design from IP Integration to implementation, Verilog RTL based IP design, Verilog/System Verilog based testbench developmentExperience with AMD Vivado & Vitis SDK & VItis AI tools.Experience with C/C++ in developing Embedded FW & scripting...
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Opening for FPGA Design role
3 days ago
bangalore, India UST Full timeHi, We have an opening for FPGA Design engineer role - Bangalore REQUIRED: EXP: 5 to 12 years Experience with FPGA system design from IP Integration to implementation, Verilog RTL based IP design, Verilog/System Verilog based testbench development Experience with AMD Vivado & Vitis SDK & VItis AI tools. Experience with C/C++ in developing Embedded FW &...
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Opening for FPGA Design role
1 day ago
bangalore, India UST Full timeHi, We have an opening for FPGA Design engineer role - Bangalore REQUIRED: EXP: 5 to 12 years Experience with FPGA system design from IP Integration to implementation, Verilog RTL based IP design, Verilog/System Verilog based testbench development Experience with AMD Vivado & Vitis SDK & VItis AI tools. Experience with C/C++ in developing Embedded FW &...
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Opening for Senior RTL design role
1 week ago
Bangalore, India UST Full timeHi Opening for RTL Design Lead role 4-12+ yrs exp, FEINT (front end integration), skill set on RTL linting, CDC/RDC checks, logic synthesis, LEC in ECO context. Please share your resume to Regards, Jaya
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Opening for Senior RTL design role
6 days ago
bangalore, India UST Full timeHi Opening for RTL Design Lead role 4-12+ yrs exp, FEINT (front end integration), skill set on RTL linting, CDC/RDC checks, logic synthesis, LEC in ECO context. Please share your resume to Regards, Jaya
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Lead Data Analyst
6 days ago
bangalore, India Open Financial Technologies Full timeJob Description : Lead Data Analyst About Open: OPEN is a leading connected finance platform that empowers finance teams to manage their cashflow better by managing all their business finance systems, right from banking to accounting ERP, payments,CRM, HRMS etc. - in one place. OPEN, India's 100th Unicorn, has been awarded the ‘Best Workplace 2024’ by...
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Opening for FPGA Verification role
2 weeks ago
bangalore district, India UST Full timeHi, Please find the JD below. FPGA Verification, 4 to 7 years of experience. Develop and implement verification plans for FPGA designs. Design and maintain testbenches for FPGA projects. Conduct functional simulations and analyze results. Collaborate with design engineers to understand design intent and constraints. Document verification processes and...
Multiple Open Roles
2 weeks ago
Capgemini Weekend Hiring Drive On Below Multiple Roles – 15th November (Saturday) 🚀 We are excited to invite talented professionals to join our team If you have expertise in Cisco technologies and are looking for your next big opportunity, this is for you. 📍 Locations: Pune | Mumbai | Bangalore | Gurgaon 🗓 Date: 15th November (Saturday)📩 Send your resumes to: ankita.a.yadav@capgemini.com | rachna.a.yadav@capgemini.com | md-ahmed.razza@capgemini.com Open Positions & Key Skills 1. L3 Security – Cisco ASA Exp: 4–9 yrs | Notice: 45 Days Cisco ASA Implementation & Design Firewall expertise (Design is a must), Identity Solutions, Email/Web Security, Cloud Security Cisco ISE is a plus 2. DC Nexus Exp: 4–9 yrs | Notice: 45 Days Hands-on with Nexus 2K/3K/5K/7K/9K R&S: IGP, OSPF, BGP, STP, VSS, vPC, VLAN, etc. CCNA/CCNP preferred 3. UCCE Exp: 4–9 yrs | Notice: 45 Days Installation & Configuration of UCCE components (ICM, CVP, CUIC, Finesse, etc.) Consulting & troubleshooting skills 4. Cisco ACI Exclusive Exp: 4–9 yrs | Notice: 45 Days Strong ACI experience, SDN knowledge Expertise in LISP, BGP, OSPF, VXLAN, CTS, etc. 5. Wireless PDI Exp: 6–10 yrs | Notice: 45 Days Implementation & migration (Aruba to Cisco, AirOS to Catalyst) RF design, WiFi 6/6E, DNAC, SDA, Meraki 6. Collaboration – CUCM Exp: 4–10 yrs | Notice: 45 Days CUCM, IMP, CUC, CER, Gateways Protocols: SIP, SCCP, MGCP, ISDN PRI, etc. ✅ Why Capgemini? Work on cutting-edge technologies, collaborate with industry experts, and grow your career in a global organization.