Senior ASIC DFT Specialist

Job Title: Lead DFT Engineer Summary:We are seeking a highly skilled and experienced DFT engineer to lead our team in the design, implementation, and verification of complex SoC/ASIC designs. As a key member of our technical team, you will be responsible for defining and driving DFT architecture, planning, and implementation across multiple projects. Key Responsibilities: Develop and implement DFT strategies and architectures for complex ASIC/SoC designsLead the implementation and verification of DFT features such as scan insertion and compression, ATPG pattern generation, fault grading, MBIST, Logic BIST, boundary scan, and IJTAGManage the end-to-end DFT flow from RTL to gate-level netlist and silicon bring-upCollaborate with cross-functional teams including RTL, STA, PD, and test engineering to ensure seamless integrationPerform pattern generation, fault simulation, and debug test coverage gapsOwn DFT signoff, timing closure, and ATE pattern deliverySupport silicon bring-up, test vector validation on ATE, and yield optimizationMentor and guide junior DFT engineers, conduct design reviews, and training sessionsDevelop and maintain DFT automation scripts and infrastructure Requirements: Bachelor's degree in Electronics, Electrical, or VLSI DesignAt least 7 years of experience in DFT for complex ASIC or SoC designsExpertise in scan insertion, compression, ATPG, MBIST, and boundary scanHands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter TestStrong knowledge of RTL design, STA, and synthesis flowsProficient in scripting languages (Python, Perl, Tcl) for flow automationDeep understanding of silicon test challenges and test coverage improvementStrong leadership, team collaboration, and communication skills Preferred Qualifications: Experience with hierarchical DFT and low-power DFT methodologies (UPF)Exposure to post-silicon validation and failure analysisFamiliarity with safety-critical designs (ISO 26262) and functional safetyExperience working in advanced nodes (e.g., 7nm, 5nm, FinFET)