Capgemini Engineering | AMS Verification Engineer | delhi
3 weeks ago
Location: Bangalore
Experience: 4 + years
Job description
• Review specifications, extract features, define and execute verification plan.
• Develop top/block level Mixed Signal and Digital testbench and generate directed/ constrained random tests
• Build and reuse real numbered analog behavioral models, monitors, and checkers for RF/Mixed-Signal blocks.
• Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage
• Write scripts for automation of flow.
• Improve Mixed Signal verification methodology.
Candidate should have:
• Verification experience with RF/Mixed-Signal blocks and SOCs.
• Good knowledge of Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc
• Good knowledge of common analog/RF blocks : ADC's, DAC's, Mixers, LDO, BIAS, PLL
• Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. digital backend for ADC, digital PLL, etc)
• Familiarity with behavioral Verilog / Verilog- A code, including wreals and RNM modeling
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