UST | Physical Design Engineer | bangalore

1 month ago

bangalore, India UST Full time

Job Title: Physical Design Engineer

Location: Bangalore/ Hyderabad


Job Summary:

We are seeking a skilled and detail-oriented Physical Design Engineer to work on the physical implementation of complex ASICs and SoCs. The role involves performing various backend design tasks, including floorplanning, placement, routing, timing closure, and power optimization, while ensuring that designs meet performance, area, and power specifications.


Key Responsibilities:


Physical Design Implementation:

  • Perform floorplanning, standard cell placement, and clock tree synthesis (CTS).
  • Conduct routing and optimize designs for performance, area, and power (PPA).

Design Verification & Closure:

  • Perform static timing analysis (STA) to achieve timing closure.
  • Resolve design rule checks (DRC), layout versus schematic (LVS), and antenna violations.
  • Ensure signal integrity and address power and thermal issues.

Power Optimization:

  • Analyze power consumption and apply optimization techniques to meet power budgets.

Collaboration:

  • Work closely with RTL design, DFT, and packaging teams to meet project goals.
  • Interact with foundries to implement and validate tapeout requirements.

Tools & Methodologies:

  • Utilize EDA tools like Synopsys ICC2, Cadence Innovus, Mentor Calibre, or similar for physical design tasks.
  • Develop and improve scripts for automation and efficiency.

Key Qualifications:

  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
  • 4+ years of experience in physical design, especially at advanced nodes (e.g., 3nm, 5nm, 7nm).

Skills:

  • Proficiency in physical design tools such as Synopsys, Cadence, or Mentor Graphics.
  • Strong understanding of STA, IR drop, power grid design, and signal integrity.
  • Knowledge of scripting languages (TCL, Python, Perl, etc.) for design automation.
  • Excellent problem-solving and debugging skills.

Preferred Qualifications:

  • Experience with full-chip integration and tapeout.
  • Knowledge of low-power design techniques.
  • Familiarity with FinFET and multi-patterning technologies.

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