Memory Layout

2 months ago


bangalore, India Tech Mahindra Full time

Hello,


We are seeking a skilled and experienced Memory Layout Engineer to join our team. The ideal candidate will have a strong background in Memory Layout and hands-on experience with industry-standard tools for Memory Layout. If you are passionate about electronics and enjoy working in a dynamic and innovative environment, we would love to hear from you.


Job Description


  • Hands-on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, decoders, etc in compiler context.
  • Hands-on experience with top-level memory integration and DRC, LVS, Density verification, and cleaning physicals across the compiler space.
  • Good handle on IR/EM-related issues in memory layouts. - Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
  • Strong knowledge of ultra-deep sub-micron layout design-related challenges and a good understanding of DFM guidelines.
  • Experience or strong interest in memory compilers developed.
  • Exp level: 3-6 years
  • Technolgy nodes : tsmc 3nm,5nm


Experience - 3+ Years

Location - Bangalore


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