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1 week ago

thiruvananthapuram, India beBeeAnalogLayout Full time

Job TitleWe are seeking an experienced Analog Layout Engineer to work on high-speed analog chip development in advanced 5nm technology.Key Responsibilities:Plan and integrate high-speed analog IPs at the chip levelPerform complete analog layout design, including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimizationRun post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematicLead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checksDrive complete IP signoff ownership, ensuring zero violations at final GDS deliveryWork closely with foundry teams for:PDK clarificationsLVS/DRC rule updatesModel issues and PEX rule discussionsTape-out requirements and signoff guidelinesCoordinate with PD, DV, circuit design, and packaging teams for smooth IP-level deliveryPrepare and deliver IP documentation, abstracts, verification reports, and GDSRequirements:8+ years of solid experience in Analog/Mixed-Signal LayoutDeep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks)Strong understanding of chip-level integration, hierarchy, and physical interfacesHands-on experience with ICC2 and top-level integration flowsAbility to run simulations for the blocks being designed (post-layout, extracted)Very detailed understanding of:IP-level verificationDRC/LVS/ERCPEX/RC extractionSignoff decks & reliability checksProven experience interacting with foundry teams for rule clarifications and IP/tape-out signoffExcellent command of Cadence Virtuoso, PVS, Calibre, and extraction toolsStrong ownership of IP delivery, customer communication, and documentationBenefits:Remote work optionTravel opportunities to the U.S. for project releaseAdditional Requirements:Experience with advanced nodes (5nm)Exposure to SERDES / PCIe / MIPI / USB high-speed IPsExperience working with global customers

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