Senior Analog Mixed Signal Verification
1 month ago
Top10 Semiconductor Organization in the World
Bangalore
What will you be doing in this role? (Responsibilities)
Responsible for developing a coverage driven verification plan by working closely with System, APPS and design team to ensure first pass silicon success
Model development using RNM/EENET
Develop test scenarios, automation and create stimulus to verify the design under test
Work with regression tools and develop scripts to submit cases for regression analysis
Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows
What do we expect from you? (Mini Qualifications)
Knowledge and Skills
Strong in Circuit Debug
Automation using Verilog AMS
Ability to debug circuit issues independently and report issues
Model development using EENET, RNM is an added advantage
Knowledge of System Verilog is an added advantage
Proficiency in Scripting languages and utilities including Python, Perl, etc.
Other
Good team player, attitude and thirst for continuous learning
Strong communication and interpersonal skills
Ability to function independently
Preferred Skills/ Experience
5+ Years’ experience in Mixed Signal verification
Skills: Virtuoso, Verilog, Verilog AMS, Cadence tools like xrun/ncsim/Vmanager
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
"Mining The Knowledge Community"
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