Senior/Lead Analog Design Engineer

7 hours ago

India Texas Instruments Full time

About the group/ team

This requirement is open for Analog Signal Chain (ASC) -Interface (INT) group at Texas Instruments India. Our charter is to develop products for Automotive and Industrial systems. These data interfaces touch our everyday lives, and the innovation and reliability we bring to these products truly make the world a safer place

Job Description:

  • Lead the design & design, development, debug and delivery of complex analog circuits/systems.
  • The main deliverable is the timely release of meticulously analysed and simulated IC designs or sub-sections of designs. These designs should lead to cost-effective, high quality, bug-free products that fully meet our customer’s end-system requirements.
  • System level understanding and analysis; and the ability to translate requirements to an IC spec
  • Must account for system level behaviour, testability, debug, characterization, production and yield targets in the IC design phase.
  • IC system partitioning and signal chain analysis, architectural tradeoff analysis
  • Block level topology selection, transistor level implementation and large/small signal analysis
  • Worst case identification, top level simulation, Monte Carlo analysis, and simulation data analysis
  • Physical layout management, signal grounding and routing trade-offs, die area optimization
  • Post layout parasitic extraction and simulation, verification of all IC level performance metrics
  • Lead top level verification, including block level modelling, top level simulation

What is required?

Strong Competency in analysis, transistor level design and implementation of several analog blocks including amplifiers, LDO’s, comparators, bandgap references, under voltage protection circutis, transmitter, receiver etc.

Architect with a top-level thought process, will need to analyze features, divide block level definitions between the sub blocks. Must excel in driving cross-team discussions and decisions to define chip-level architecture.

Be open to learn and design for EMC, ESD, Surge, EFT kind of system level specifications for automotive and industrial transceivers

  • Verification of Blocks across PVT, Statistical mismatch.
  • Mixed-Mode top-level verification using tools such as Cadence AMS
  • Behavioral Modelling of analog blocks in Verilog AMS.
  • A good understanding of Device Physics, an ability to evaluate process technologies, and pick the right process, right components
  • Organizational Skills:
  • Ability to lead a team of design/DV/layout engineers during the project
  • Ability to work well with internal cross functional teams (systems, test, digital design, verification, validation, applications, marketing, etc.) to resolve issues and generate business success.
  • Problem solving and communication (written and oral) are important skills in this role.
  • Must be able to manage assigned tasks with minimal supervision.
  • Deep understanding of semiconductor IC processing, semiconductor packaging, and production test solutions is highly desirable.
  • Familiarity with mid-high voltage (20-70V),analog design is definitely a plus.

Minimum requirements:

  • B.E/B.tech/MTech/MS or higher
  • Analog Circuit design knowledge
  • Process and Device Physics understanding
  • 3-10 years of experience in Analog mixed signal design
  • Familiarity and interest in Systems, Signal chains

Soft Skills:

  • Passion, Self-drive, Hard work, Willingness to learn

Why TI?

  • Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.
  • We’re different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours.
  • Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us.

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