Senior Semiconductor Designer

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Principal Digital Forensic Engineer Drive the design and implementation of digital forensic architecture for complex semiconductor designs.Main Responsibilities:Elevate digital forensic strategy and architecture for multiple projects, overseeing key features like scan insertion and compression, ATPG pattern generation, MBIST, Logic BIST, boundary scan, IJTAG, and more.Oversee end-to-end digital forensic flow from RTL to gate-level netlist and silicon bring-up, ensuring seamless integration with RTL, STA, PD, and test engineering teams.Implement pattern generation, fault simulation, and debug test coverage gaps, ensuring DFT signoff, timing closure, and ATE pattern delivery.Mentor junior engineers, conduct design reviews, and develop automation scripts and infrastructure.Ensure compliance with industry requirements and standards.Develop and implement strategies for silicon bring-up, test vector validation on ATE, and yield optimization. Key qualifications include a degree in Electronics, Electrical Engineering or VLSI Design, 7+ years of experience in digital forensic engineering for complex ASIC or SoC designs, expertise in various techniques, and proficiency in scripting languages like Python, Perl, and Tcl for flow automation.

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