Digital Fault Tolerance Engineer

2 days ago


shimoga, India beBeeDft Full time

Technical Lead - Digital Fault Tolerance EngineeringWe are seeking an experienced technical lead to drive digital fault tolerance engineering across our complex SoC/ASIC designs.Promote and implement best practices in DFT architecture, planning, and implementation.This role requires close collaboration with cross-functional teams to ensure world-class testability and manufacturability of silicon products.Evaluate and improve existing DFT strategies and architectures for multiple ASIC/SoC projects.Develop and maintain a deep understanding of advanced technologies such as scan insertion, compression, ATPG, MBIST, and boundary scan.The ideal candidate will possess strong leadership skills, excellent team collaboration, and communication abilities, along with experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Key Qualifications:Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.At least 7 years of experience in DFT for complex ASIC or SoC designs.Essential Skills:Expertise in pattern generation, fault simulation, and debug test coverage gaps.Strong analytical and problem-solving skills, with ability to manage multiple priorities and deadlines.



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