Senior Digital Fault Tolerant Engineer

2 weeks ago


shimoga, India beBeeDftLead Full time

Job DescriptionA seasoned professional with 7 to 15 years of experience is required for this challenging role. The ideal candidate will possess in-depth knowledge of DFT concepts, scan insertion, ATPG, coverage analysis, transition delay test coverage analysis, MBIST insertion, memory test validation, test mode timing constraints definition, scripting languages, RTL and gate level simulations, equivalence check, DFT DRC rules, and working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test.



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