Chief Digital Fault Test Architect

2 days ago

bhavnagar, India beBeeDigitalFaultTest Full time

Job OverviewWe are seeking an experienced Digital Fault Test Engineer to lead the development and implementation of digital fault test (DFT) strategies for complex system-on-chip (SoC) and application-specific integrated circuit (ASIC) designs.The ideal candidate will have a strong background in DFT, with expertise in scan insertion, compression, ATPG pattern generation, fault grading, MBIST, logic BIST, boundary scan, and IJTAG. They will also possess excellent communication and leadership skills to work effectively with cross-functional teams.Key ResponsibilitiesDevelop and drive DFT strategy and architecture for multiple SoC/ASIC projects.Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.

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