Expert DFT Strategist

4 days ago

bhavnagar, India beBeeDigitalFaultToleranceEngineer Full time

Senior Architect of Digital Fault ToleranceAbout the Role: We are seeking a seasoned expert to spearhead the development and implementation of digital fault tolerance strategies across our complex SoC/ASIC designs.Key Responsibilities:Define and execute comprehensive DFT architectures for multiple projects, ensuring seamless integration with cross-functional teams.Develop and verify advanced DFT features, including but not limited to: scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, Boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).Oversee the end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up, optimizing test coverage and efficiency.Collaborate closely with design teams to ensure timely delivery and flawless execution of DFT-related tasks.Perform in-depth analysis and simulation to identify and rectify test coverage gaps, guaranteeing highest possible yields.Own and drive DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery processes.Play a key role in silicon bring-up, test vector validation on ATE, and yield optimization efforts.Mentor junior engineers, conduct technical reviews, and develop automation scripts and infrastructure to streamline DFT processes.

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