RTL Design

1 month ago


hyderabad, India BITSILICA Full time

We are currently seeking experienced RTL Engineers

- Minimum 4 years of experience required

- Proficiency in RTL development from micro-architecture

- Expertise in SoC, Memory, Peripheral, Security, and Cache IP’s Analysis & Integration

- Skilled in RTL Quality checks including VCS, synthesis checks, LINT, LEC, CDC

- Strong background in Failures Debug/Bug fixes on RTL and Netlist

- Experience in low-level design document generation, implementation & review

- Knowledge of ARM Cortex based system understanding & Integration

Join our dynamic team to collaborate on cutting-edge projects and contribute to innovative solutions in semiconductor design

Interested candidates, please share your resume with suman.ragothama@bitsilica.com


  • Rtl design

    2 months ago


    Hyderabad, India BITSILICA Full time

    We are currently seeking experienced RTL Engineers - Minimum 4 years of experience required - Proficiency in RTL development from micro-architecture - Expertise in So C, Memory, Peripheral, Security, and Cache IP’s Analysis & Integration - Skilled in RTL Quality checks including VCS, synthesis checks, LINT, LEC, CDC - Strong background in Failures...

  • RTL Design

    1 month ago


    hyderabad, India BITSILICA Full time

    We are currently seeking experienced RTL Engineers- Minimum 4 years of experience required- Proficiency in RTL development from micro-architecture- Expertise in SoC, Memory, Peripheral, Security, and Cache IP’s Analysis & Integration- Skilled in RTL Quality checks including VCS, synthesis checks, LINT, LEC, CDC- Strong background in Failures Debug/Bug...

  • RTL Design

    2 months ago


    Hyderabad, India BITSILICA Full time

    We are currently seeking experienced RTL Engineers- Minimum 4 years of experience required- Proficiency in RTL development from micro-architecture- Expertise in SoC, Memory, Peripheral, Security, and Cache IP’s Analysis & Integration- Skilled in RTL Quality checks including VCS, synthesis checks, LINT, LEC, CDC- Strong background in Failures Debug/Bug...

  • RTL Design

    2 months ago


    hyderabad, India BITSILICA Full time

    We are currently seeking experienced RTL Engineers - Minimum 4 years of experience required - Proficiency in RTL development from micro-architecture - Expertise in SoC, Memory, Peripheral, Security, and Cache IP’s Analysis & Integration - Skilled in RTL Quality checks including VCS, synthesis checks, LINT, LEC, CDC - Strong background in Failures Debug/Bug...

  • RTL Design

    2 months ago


    hyderabad, India BITSILICA Full time

    We are currently seeking experienced RTL Engineers - Minimum 4 years of experience required - Proficiency in RTL development from micro-architecture - Expertise in SoC, Memory, Peripheral, Security, and Cache IP’s Analysis & Integration - Skilled in RTL Quality checks including VCS, synthesis checks, LINT, LEC, CDC - Strong background in Failures Debug/Bug...

  • RTL Design Engineer

    4 weeks ago


    hyderabad, India BITSILICA Full time

    Experience range : 4+ Yrs and above only(no freshers please)Work Location : HyderabadNotice : Immediate to 15 daysJob Scope:- RTL development from micro-architecture- SoC, Memory, Peripheral, Security and Cache IP’s Analysis & Integration- RTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC)- Failures Debug/Bug fixes on RTL and Netlist- Low level...

  • RTL Design Engineer

    3 months ago


    hyderabad, India BITSILICA Full time

    Experience range : 4+ Yrs and above only(no freshers please) Work Location : Hyderabad Notice : Immediate to 15 days Job Scope: RTL development from micro-architecture SoC, Memory, Peripheral, Security and Cache IP’s Analysis & Integration RTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC) Failures Debug/Bug fixes on RTL and Netlist Low level...

  • Rtl design engineer

    2 months ago


    Hyderabad, India BITSILICA Full time

    Experience range : 4+ Yrs and above only(no freshers please) Work Location : Hyderabad Notice : Immediate to 15 days Job Scope: RTL development from micro-architecture So C, Memory, Peripheral, Security and Cache IP’s Analysis & Integration RTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC) Failures Debug/Bug fixes on RTL and Netlist Low...

  • RTL Design Engineer

    3 months ago


    hyderabad, India BITSILICA Full time

    Experience range : 4+ Yrs and above only(no freshers please)Work Location : HyderabadNotice : Immediate to 15 daysJob Scope:RTL development from micro-architectureSoC, Memory, Peripheral, Security and Cache IP’s Analysis & IntegrationRTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC)Failures Debug/Bug fixes on RTL and NetlistLow level design...

  • RTL Design Engineer

    1 month ago


    hyderabad, India BITSILICA Full time

    Experience range : 4+ Yrs and above only(no freshers please)Work Location : HyderabadNotice : Immediate to 15 daysJob Scope:RTL development from micro-architectureSoC, Memory, Peripheral, Security and Cache IP’s Analysis & IntegrationRTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC)Failures Debug/Bug fixes on RTL and NetlistLow level design...

  • Rtl design engineer

    1 month ago


    Hyderabad, India BITSILICA Full time

    Experience range : 4+ Yrs and above only(no freshers please)Work Location : HyderabadNotice : Immediate to 15 daysJob Scope:RTL development from micro-architectureSo C, Memory, Peripheral, Security and Cache IP’s Analysis & IntegrationRTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC)Failures Debug/Bug fixes on RTL and NetlistLow level design...


  • Hyderabad, Telangana, India UST Full time

    UST Seeks Experienced RTL Synthesis ExpertWe are looking for a seasoned RTL synthesis professional to join our team at UST. The ideal candidate will have extensive experience in RTL design, analysis, and optimization using industry-leading tools.About the Role:Design, implement, and verify complex digital circuits using RTL synthesis techniques.Collaborate...

  • RTL Design Engineer

    3 months ago


    hyderabad, India BITSILICA Full time

    Experience range : 4+ Yrs and above only(no freshers please) Work Location : Hyderabad Notice : Immediate to 15 days Job Scope: RTL development from micro-architecture SoC, Memory, Peripheral, Security and Cache IP’s Analysis & Integration RTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC) Failures Debug/Bug fixes on RTL and Netlist Low level...

  • RTL Design Engineer

    4 months ago


    Hyderabad, India BITSILICA Full time

    Experience range : 4+ Yrs and above only(no freshers please) Work Location : Hyderabad Notice : Immediate to 15 days Job Scope: RTL development from micro-architecture SoC, Memory, Peripheral, Security and Cache IP’s Analysis & Integration RTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC) Failures Debug/Bug fixes on RTL and Netlist Low level...

  • RTL Design Engineer

    3 months ago


    hyderabad, India BITSILICA Full time

    Experience range : 4+ Yrs and above only(no freshers please)Work Location : HyderabadNotice : Immediate to 15 days Job Scope: RTL development from micro-architectureSoC, Memory, Peripheral, Security and Cache IP’s Analysis & IntegrationRTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC)Failures Debug/Bug fixes on RTL and NetlistLow level design...

  • RTL Design Engineer

    4 months ago


    Hyderabad, India BITSILICA Full time

    Experience range : 4+ Yrs and above only(no freshers please)Work Location : HyderabadNotice : Immediate to 15 days Job Scope: RTL development from micro-architectureSoC, Memory, Peripheral, Security and Cache IP’s Analysis & IntegrationRTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC)Failures Debug/Bug fixes on RTL and NetlistLow level design...

  • RTL Design Engineer

    2 months ago


    hyderabad, India BITSILICA Full time

    Experience range : 4+ Yrs and above only(no freshers please) Work Location : Hyderabad Notice : Immediate to 15 days Job Scope: RTL development from micro-architecture SoC, Memory, Peripheral, Security and Cache IP’s Analysis & Integration RTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC) Failures Debug/Bug fixes on RTL and Netlist Low level...


  • hyderabad, India Sevya Multimedia Full time

    RTL Design Engineers at Hyderabad We need experienced engineers to work on cutting edge technology and with complex functionality. Skills: Overall 3+ years industry experience with 2+ years in RTL Design and SoC Integration. Proven hands-on experience with RTL design for IP, the subsystem for ASIC. Hands-on experience with SoC integration issues like...


  • Hyderabad, India Sevya Multimedia Full time

    RTL Design Engineers at Hyderabad We need experienced engineers to work on cutting edge technology and with complex functionality. Skills: Overall 3+ years industry experience with 2+ years in RTL Design and So C Integration. Proven hands-on experience with RTL design for IP, the subsystem for ASIC. Hands-on experience with So C integration...


  • hyderabad, India Sevya Multimedia Full time

    RTL Design Engineers at HyderabadWe need experienced engineers to work on cutting edge technology and with complex functionality.Skills:Overall 3+ years industry experience with 2+ years in RTL Design and SoC Integration.Proven hands-on experience with RTL design for IP, the subsystem for ASIC.Hands-on experience with SoC integration issues like clocking,...