Digital Fault Tolerance Engineer

1 week ago

Jamnagar, India beBeeDft Full time

Senior DFT ArchitectOverview:We seek a technical leader to drive digital fault tolerance architecture, planning, and implementation across complex system-on-chip (SoC) designs.Key responsibilities include defining and driving DFT strategy and architecture for multiple projects, leading implementation and verification of DFT features like scan insertion and compression, ATPG pattern generation and fault grading, memory BIST and logic BIST insertion and validation, boundary scan, and IJTAG.Manage end-to-end DFT flow from register-transfer level (RTL) to gate-level netlist and silicon bring-up.Collaborate with RTL, static timing analysis, physical design, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure, and automatic test equipment (ATE) pattern delivery.Requirements:Bachelor's or master's degree in electronics, electrical, or VLSI design.Seven or more years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, memory BIST, and boundary scan.Preferred Qualifications:Experience with hierarchical DFT and low-power DFT methodologies.Exposure to post-silicon validation and failure analysis.

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    Jamnagar, India beBeeDigitalFaultTolerance Full time

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