Senior Analog Layout Design Engineer

1 week ago

vadodara, India beBeeAnalog Full time

Job SummaryWe are seeking a seasoned Analog Layout Engineer to join our team and play a key role in the development of high-speed analog chip technology. The ideal candidate will have deep technical expertise in chip-level integration, hierarchy, and physical interfaces.The successful candidate will be responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision. This requires strong understanding of circuit simulation concepts, ICC2 flows, and top-level integration.The engineer will work closely with SoC, Circuit, and Digital teams to ensure robust layout quality and performance. Additionally, they will lead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checks.Key Responsibilities:Chip-level planning and integration of high-speed analog IPsPerform complete analog layout design, including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimizationRun post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematicStrong understanding of ICC2 flows for complete SoC/top-level integrationLead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checksDrive complete IP signoff ownership, ensuring zero violations at final GDS deliveryRequired Skills and Qualifications:8+ years of solid experience in Analog/Mixed-Signal LayoutDeep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks)Strong understanding of chip-level integration, hierarchy, and physical interfacesHands-on experience with ICC2 and top-level integration flowsAbility to run simulations for the blocks being designed (post-layout, extracted)Very detailed understanding of IP-level verification, DRC/LVS/ERC, PEX/RC extraction, signoff decks & reliability checksBenefits:Competitive salary packageOpportunity to work on cutting-edge projectsCollaborative and dynamic work environmentOthers:Mandatory experience in TSMC 5NM. Excellent command of Cadence Virtuoso, PVS, Calibre, and extraction tools. Strong ownership of IP delivery, customer communication, and documentation.

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