Principal Circuit Design Specialist

1 week ago


vadodara, India beBeeAnalog Full time

Our company is seeking a highly skilled Senior Analog Layout Engineer to lead the design and integration of high-speed analog IPs at the chip level.As a key member of our team, you will be responsible for developing and verifying complex analog layouts, ensuring compliance with strict design rules and standards.Key Responsibilities:Analog Layout & IntegrationLead chip-level planning and integration of high-speed analog IPs.Execute complete analog layout design including floor planning, routing, device matching, shielding, EM/IR checks, and parasitic optimization.Run post-layout simulations (corners, Monte Carlo, extracted netlist) and ensure correlation with schematic.IP Verification & SignoffOwn the entire IP verification process: DRC, LVS, ERC, ANT, PEX, and reliability checks.Ensure zero-violation GDS delivery for IP signoff.Work closely with foundry teams on PDK clarifications, rule updates, model issues, PEX discussions, and tape-out requirements.Cross-Functional CollaborationCoordinate with PD, DV, circuit design, packaging, and integration teams for seamless IP delivery.Prepare and deliver comprehensive IP documentation, abstracts, verification reports, and final GDS.Required Skills and Qualifications:8+ years of proven experience in Analog/Mixed-Signal Layout.Deep expertise in high-speed IPs: SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks.Strong understanding of chip-level hierarchy, integration, and physical interfaces.Proficiency in Cadence Virtuoso, PVS, Calibre, and extraction tools.In-depth knowledge of:DRC/LVS/ERCPEX & RC ExtractionSignoff decks and reliability checks



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