Director, Digital Engineering,
2 weeks ago
SOC design/ integration, including RTL, SDC integration and relative checks including
CDC, nLint,
clock/reset/mixed mode/DFT architecture, design and verification.Oversee the chip design flow including the whole chip synthesis, DFT(SCAN/MBIST) insertion, LEC and
STA, timing closure.Lead the FPGA synthesis and verification process.Collaborate with cross-functional teams and lead the BT SoC projectsLead the final stage of chip development, including tape-out preparation and execution; handle transition from design to transition from design to mass production.CompetenciesProactive, self-starter, able to work independently in a fast-paced environmentWell organized with strong attention to detail; proactively ensures work is accuratePositive attitude and work ethic; unafraid to ask questions and explore new ideasAble to solve routine problems through practical use of technologyAbility to work within a diverse teamTeam builder and strong leader – hiring and developing talent, vision to inspire and excite team, and management of performanceExperience in working collaboratively and leading a diverse, global cross-functional teamPassionate about building great products and solving customer and business problemsAbility to rapidly learn new technologiesAnalytical with strong business acumen and able to make informed decisions based on experienceDemonstrated ability to use data to improve processes and evaluate design optionsExcellent organizational, planning, and documentation skills with high attention to detailExcellent verbal and written communication that is clear, concise, and compellingQualifications
(Requirements)MS degree in Computer Engineering, Communication or Electrical/Electronic Engineering.15-20 years of experience in digital IC design and Verilog coding including leading teams.Familiar with at least one of the followings: computer architecture,
MCU peripherals,
Wi-Fi
and
Bluetooth.Familiarity with digital IC design flow (design, verification, synthesis, HW/SW co-working) and FPGA synthesis and verification flow.Solid tape out experiences
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