Senior Verification Engineer

Senior Verification Engineer - Location: Bangalore/Hyderabad - Experience: 4+ years - 1Must have very good System Verilog/UVM experience - Must have expertise in PCI gen6 and CXL3.1or Ethernet bus protocols - Have experience in IP/SoC Verification - Expertise in AMBA/AXI bus protocols and ARM CPU - Experience in developing functional verification...

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ Ahmedabad ROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches. Highly experienced with defining block, sub-system and SOC top level test plans. Relevant experience with one or more of PCIe,...

Senior Design Verification Engineer: Should have PCIE IP level verification exposure Good UVM understanding Serial protocol understanding Interested,please drop your updated CV to

Senior Design Verification Engineer: Should have PCIE IP level verification exposure Good UVM understanding Serial protocol understanding Interested,please drop your updated CV to

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ AhmedabadROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches.Highly experienced with defining block, sub-system and SOC top level test plans.Relevant experience with one or more of PCIe, NVMe, NAND, DDR and...

Senior Design Verification Engineer:Should have PCIE IP level verification exposureGood UVM understandingSerial protocol understandingInterested,please drop your updated CV to janagaradha.n@acldigital.com

Position Overview: We are seeking a highly skilled Senior Engineer/Architect to join our dynamic team. In this pivotal role, you will lead the design and verification of advanced integrated circuits (ICs), ensuring they meet the highest standards of quality and performance. This position offers the opportunity to work on groundbreaking projects and influence...

Senior Design verification Engineer Mandatory Skill : PCIE Location : Bangalore Experience : 5 years Design Verification Engineer responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/SystemVerilog to create testbenches, write...

Hi All, ACL Digital is hiring #Senior #Design #Verification Engineer! Experience: 4 Years Location: Bangalore / Hyderabad Notice Period: Immediate to 30 Days Preferred! We're seeking experienced professionals ASIC/SoC verification. If you have expertise in UVM/System Verilog, proficiency in scripting languages like Python/Perl/TCL, and a strong...

Senior Verification EngineerLocation: Bangalore/HyderabadExperience: 4+ years1Must have very good System Verilog/UVM experienceMust have expertise in PCI gen6 and CXL3.1or Ethernet bus protocolsHave experience in IP/SoC VerificationExpertise in AMBA/AXI bus protocols and ARM CPUExperience in developing functional verification environments including the...