RTL Design Engineer

4 days ago

hyderabad, India Proxelera Full time

We’re hiring an RTL Design Lead who can own front-end SoC architecture, guide technical direction, and drive RTL execution from spec to handoff. You’ll lead micro-architecture definition, ensure clean and efficient RTL, and collaborate across DV, PD, DFT, and architecture teams to deliver high-quality silicon.Job Description:Lead RTL design and micro-architecture for complex SoC/IP blocks, ensuring PPA-optimized and synthesizable SystemVerilog/Verilog RTL.Drive IP integration, synthesis readiness, and design closure using LINT, CDC/RDC, SDC, and low-power (UPF/CPF) methodologies.Collaborate with DV, PD, DFT, analog, and architecture teams to resolve design, timing, and integration issues across the full front-end flow.Guide junior engineers through reviews, architectural decisions, and best-practice RTL processes while ensuring clean handoff to downstream teams.For engineers who want full ownership of RTL design and the opportunity to guide SoC projects from architecture to tapeout, this position offers real influence.Cheers,Karthik Kumarkarthik.adasu@proxelera.com

  • Senior ASIC RTL Designer

    2 weeks ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    2 weeks ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    2 weeks ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    2 weeks ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years - Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. - Create micro-architecture specs and ensure designs meet performance, power, and area targets. - Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA,...

  • Senior ASIC RTL Designer

    2 weeks ago

    hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    2 weeks ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    2 weeks ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

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    5 days ago

    Hyderabad, India Proxelera Full time

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  • RTL Design Engineer

    4 days ago

    Hyderabad, India Proxelera Full time

    We’re hiring an RTL Design Lead who can own front-end SoC architecture, guide technical direction, and drive RTL execution from spec to handoff. You’ll lead micro-architecture definition, ensure clean and efficient RTL, and collaborate across DV, PD, DFT, and architecture teams to deliver high-quality silicon.Job Description:Lead RTL design and...

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