Senior Memory Layout Engineer

1 week ago

bareilly, India beBeeMemoryLayout Full time

Optimize Memory Layouts for Cutting-Edge CoresWe are seeking a skilled Memory Layout Specialist to develop innovative memory compilers layouts and optimize memory Fast Cache instances layouts for our next-generation processor architectures.To succeed in this role, you will need to have a strong understanding of CMOS transistor behavior, as well as basic knowledge of CMOS logic design and layout principles. Additionally, you should be able to create high-quality design rule-driven layouts, review schematics with engineers, and propose changes based on layout implications.Experience with scripting languages such as Perl or Python is a plus, and some experience working on Cadence or Synopsys flows can be beneficial.Key aspects of the job include:Developing memory compilers layouts that achieve outstanding performance, power, and area (PPA) efficiency.Collaborating with engineering teams to review and optimize layout designs.Proposing changes to layout implications and contributing to the development of new layout methodologies.The ideal candidate will have a strong foundation in CMOS transistor behavior, CMOS logic design, and layout principles. Additionally, experience with scripting languages and familiarity with Cadence or Synopsys flows can be advantageous. If you are passionate about developing innovative memory layouts and collaborating with cross-functional teams, we encourage you to apply.

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    bareilly, India beBeeMemory Full time

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    bareilly, India beBeeAnalog Full time

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    bareilly, India beBeeLayout Full time

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