High-Speed Analog Layout Specialist

2 weeks ago

bareilly, India beBeeAnalog Full time

Job Title: Senior Analog Layout EngineerWe are seeking an experienced Senior Analog Layout Engineer to join our team. As a Senior Analog Layout Engineer, you will be responsible for designing and integrating high-speed analog IPs at the chip level.The ideal candidate will have strong expertise in ICC2-based top-level integration, extensive IP verification experience, and the ability to run block-level simulations independently.This role requires deep knowledge of DRC/LVS/ERC, PEX & RC Extraction, Signoff decks, and reliability checks.You will work closely with foundry teams on PDK clarifications, rule updates, model issues, PEX discussions, and tape-out requirements.Additionally, you will coordinate with PD, DV, circuit design, packaging, and integration teams for seamless IP delivery.Key Responsibilities:Analog Layout & Integration:Lead chip-level planning and integration of high-speed analog IPs.Execute complete analog layout design including floor planning, routing, device matching, shielding, EM/IR checks, and parasitic optimization.Run post-layout simulations (corners, Monte Carlo, extracted netlist) and ensure correlation with schematic.IP Verification & Signoff:Own the entire IP verification process: DRC, LVS, ERC, ANT, PEX, and reliability checks.Ensure zero-violation GDS delivery for IP signoff.Cross-Functional Collaboration:Coordinate with PD, DV, circuit design, packaging, and integration teams for seamless IP delivery.Prepare and deliver comprehensive IP documentation, abstracts, verification reports, and final GDS.Process & Technology Expertise:Mandatory hands-on experience with TSMC 5nm.Strong understanding of ICC2 flows for complete SoC/top-level integration.Required Skills:8+ years of proven experience in Analog/Mixed-Signal Layout.Deep expertise in high-speed IPs: SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks.Strong understanding of chip-level hierarchy, integration, and physical interfaces.

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