Staff Engineer, ASIC Development Engineering

6 days ago

bangalore, India Western Digital Full time
Job Description

We are seeking a highly skilled Analog/IO Layout Engineer with 5-10 years of experience to design and implement complex analog and mixed-signal IC layouts. The ideal candidate will have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems.

Key Responsibilities:

  • Develop and optimize analog and mixed-signal IC layouts, ensuring high performance and manufacturability.
  • Collaborate with design engineers to understand design requirements and translate them into precise layouts.
  • Strong experience in debugging DRC, ERC,LVS and PERC issues independently.
  • Work closely with the physical design team to integrate analog/IO blocks into the overall chip design.
  • Identify and resolve layout-related issues, providing creative solutions to meet design specifications.
  • Conduct design reviews and provide technical feedback to improve layout practices and methodologies.
  • Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes.

Qualifications
  • Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field.
  • 5-10 years of experience in analog and mixed-signal IC layout design.
  • Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics.
  • Hands-on experience with custom layout design for various analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs, and ESD circuits.
  • Familiarity with custom digital layout (i.e. high speed logic paths).
  • Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding).
  • Strong understanding of analog/IO design principles, including circuit performance and parasitic effects.
  • Aware of layout techniques to mitigate ESD, latch-up issues.
  • Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 7nm and below.
  • Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating.
  • Experience with layout optimization for power, performance, and area (PPA) metrics.
  • Excellent problem-solving skills and attention to detail.
  • Effective communication and teamwork abilities.

Preferred Skills:

  • Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks.

Additional Information

Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at staffingsupport@wdc.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

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