ASIC Design Verification Engineer
3 weeks ago
Role Overview: We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology. The ideal candidate will have hands-on experience in SoC and IP-level verification across multiple domains, along with good scripting skills. Exposure to C language is a plus. Key Responsibilities: - Develop and execute verification plans for SoC and IP-level designs. - Build and maintain test benches using System Verilog and UVM. - Perform functional verification, including simulation, coverage analysis, and debugging. - Collaborate with design and architecture teams to ensure verification completeness. - Automate verification flows using scripting languages (Python, Perl, Shell, etc.). - Analyze and report coverage metrics and ensure compliance with verification goals. Required Skills: - 4-20 years experience in ASIC Design Verification. - Strong knowledge of System Verilog and UVM methodology. - Hands-on experience in SoC and IP-level verification across domains such as: - Automotive - Audio - Networking - High-Speed Interfaces (PCIe, Ethernet, USB) - Memory Subsystems (DDR, LPDDR) - Processor Subsystems (ARM, RISC-V) - Proficiency in scripting languages (Python, Perl, Shell). - Good understanding of verification concepts, coverage, and debugging techniques. Good to Have: - Exposure to C programming for embedded or verification-related tasks. - Familiarity with formal verification and low-power verification methodologies. - Experience with industry-standard EDA tools (Synopsys VCS, Cadence Xcelium, Mentor Questa). Education: Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Engineering or related field.
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ASIC Design Verification Engineer
1 day ago
Jamnagar, India Tata Consultancy Services Full timeRole Overview: We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology. The ideal candidate will have hands-on experience in SoC and IP-level verification across multiple domains, along with good scripting skills. Exposure to C language is a plus. Key Responsibilities: - Develop and...
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Design Verification Engineer
4 days ago
Jamnagar, India Best NanoTech Full timePosition: Senior DV EngineerWe’re looking for an experienced DV engineer to lead SOC Design Verification for complex, high-performance projects.About the RoleExperience - 7+ YearsLocation - Pune/Bangalore/AhmedabadResponsibilities- Drive SOC verification execution and ensure successful delivery of verification plans.- Develop and implement robust...
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Senior Design Verification Expert
4 days ago
Jamnagar, India beBeeVerification Full timeJob OverviewWe are seeking an experienced senior design verification professional to lead our SoC design verification efforts.The ideal candidate will have a strong track record of successfully executing verification plans, developing and implementing comprehensive verification strategies, and collaborating with cross-functional teams.Responsibilities:Lead...
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Senior Physical Design Engineer
6 days ago
Jamnagar, India Eximietas Design Full timeHi All,Eximietas Hiring Senior Physical Design Leads/Managers.Experience: 10+ Years.Locations:Bengaluru, IndiaVisakhapatnam, IndiaSan Jose (Bay Area), USAAustin, USAEligibility (US Roles): Valid H1B or candidates already in the U.S.About the jobQualification Required:Typically requires a minimum of 10+ years of experience in Physical Design with mainstream...
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Senior Verification Lead
4 days ago
Jamnagar, India beBeeVerification Full time**Job Description:**We are seeking an experienced Senior Verification Engineer to lead our SOC Design Verification efforts for complex projects.The successful candidate will be responsible for managing verification plans, developing comprehensive verification strategies, and creating test plans and test benches for high-speed SOCs.**Required Skills and...
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Digital Fault Tolerance Engineer
7 days ago
Jamnagar, India beBeeDft Full timeSenior DFT ArchitectOverview:We seek a technical leader to drive digital fault tolerance architecture, planning, and implementation across complex system-on-chip (SoC) designs.Key responsibilities include defining and driving DFT strategy and architecture for multiple projects, leading implementation and verification of DFT features like scan insertion and...
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Senior Test Development Engineer
24 hours ago
Jamnagar, India beBeeArchitect Full timeLead DFT ArchitectWe are seeking a highly skilled DFT Architect to drive the development of advanced test and debug technologies for complex SoC/ASIC designs.Define and execute a comprehensive DFT strategy for multiple ASIC/SoC projects, ensuring seamless integration with RTL, STA, PD, and test engineering teams.Develop and implement cutting-edge test...
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Senior Embedded Systems Designer
1 week ago
Jamnagar, India beBeeHardware Full timeHardware Engineering PositionWe are seeking a skilled Hardware Engineer to collaborate with our research team in developing cutting-edge hardware solutions for AI training environments. As a key member of our team, you will create high-quality RTL design and verification challenges that mirror real-world semiconductor development.Develop realistic RTL design...
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Senior Physical Design Engineer
4 days ago
Jamnagar, India beBeePhysicalDesigner Full timeAbout the Position:We are seeking a seasoned expert in Physical Design to lead our team of engineers and contribute to the development of cutting-edge semiconductor products.Our ideal candidate will have extensive experience working on designs at 10nm/7nm/5nm or lower nodes with various customers, utilizing mainstream P&R tools.They will be responsible for...
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High Speed Analog Engineering Specialist
1 week ago
Jamnagar, India beBeeExpertise Full timeJob Title:Senior Analog Layout EngineerAbout the JobWe are seeking a highly experienced Senior Analog Layout Engineer with strong expertise in chip-level handling of high-speed analog IPs, deep understanding of ICC2-based top-level integration, and the ability to independently run block-level simulations.This role demands full ownership of IP development,...