BITSILICA - Verification Engineer - SoC/GLS

Key Responsibilities :- Develop comprehensive verification plans and strategies for SoC and GLS components.- Design, implement, and maintain reusable testbenches using SystemVerilog and UVM methodologies.- Perform functional verification of AMBA bus protocols including AXI, AHB, and APB.- Collaborate with RTL designers and architects to understand...

Key ResponsibilitiesDevelop comprehensive verification plans and strategies for SoC and GLS components.Design, implement, and maintain reusable testbenches using SystemVerilog and UVM methodologies.Perform functional verification of AMBA bus protocols including AXI, AHB, and APB.Collaborate with RTL designers and architects to understand specifications and...

URGENT OPENING: Design Verification Engineer | Hyderabad | BITSILICACalling all Verification expertsReady for your next challenge? What we need: 6+ Years of DV experience Deep verification expertise Passion for complex problem-solving What you'll do: Lead verification projects Work with state-of-the-art tools Collaborate with global teams Drive innovation in...

Job Description:We're looking for a verification SME, responsible for the SoC verification process and designing the next-generation HBM DRAM products. Deep understanding of SoC Verification, testbench architecture, SoC verification methodologies, and 2.5D & 3D package integration.Responsibilities: • Develop test plans at SOC Level and analyze Coverage....

About SpanIdea systems: SpanIdea Systems is a globalproduct engineering solutions and services company, headquartered in Bangalore with development centers across India, the US, and Europe. Founded in 2011, the company partners with Fortune 500 clients to deliver solutions inembedded systems, semiconductors, telecom, networking, IoT, cloud, and mobility....

Over 10 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good...

Over 3 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good in...

Over 3 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flowProficient with Verilog, System Verilog and UVM.· Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard)· Good in defining and developing UVM based verification frameworks, testbenches, processes and flows.· Good in...

Over 3 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flowProficient with Verilog, System Verilog and UVM.· Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard)· Good in defining and developing UVM based verification frameworks, testbenches, processes and flows.· Good in...

Over 8 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and System Verilog language. (SVA, UVM scoreboard)· Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good...