▷ [11/10/2025] Verification Engineer - UVM/System Verilog

his is what you are responsible for :- Develop and maintain verification plans, testbenches, and test cases for ASIC designs.- Collaborate with design and architecture teams to understand design specifications and requirements.- Design and implement System Verilog/UVM-based verification environments.- Create and execute test cases to verify functionality,...

Key Responsibilities - AMS Verification- Work in Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs.- Hands-on experience with AMS simulation environments using Cadence, Synopsys, or Mentor tools.- Solid understanding of analog and mixed-signal circuits, including - comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors,...

About the Role : We are seeking a talented Senior ASIC Verification Engineer to join our dynamic team. The successful candidate will be responsible for leading and executing verification efforts for complex ASIC designs, ensuring the quality and reliability of our products.This is what you are responsible for : - Develop and maintain verification plans,...

Job Description Minimum qualifications: - Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. - 4 years of experience verifying digital logic at RTL using SystemVerilog for ASICs. - Experience verifying digital systems using standard IP components/interconnects (microprocessor cores or hierarchical memory...

Over 10 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flowProficient with Verilog, System Verilog and UVM.· Good in UVM concepts and System Verilog language. (SVA, UVM scoreboard)· Good in defining and developing UVM based verification frameworks, testbenches, processes and flows.· Good in...

Job Description Lead Verification Engineer SoC Verification Engineer >> Lead Verification Engineer Post Lead Verification Engineer Required Experience 7 to 12 years Location: Bangalore,Delhi NCR,Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Must haves: Worked on IP and SOC level verification 7-12 years of...

SSOC Design Verification Engineer - Senior / Lead / Sr. LeadExperience: 5 to 12 YearsLocation: Hyderabad / BangaloreJob Requirement- Must have good knowledge on the verification flows - Excellent hands-on debug skills and problem solving attitude. - Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC. - Experience of...

BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...

Over 10 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flowProficient with Verilog, System Verilog and UVM.· Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard)· Good in defining and developing UVM based verification frameworks, testbenches, processes and flows.· Good in...

We need experienced engineers to verify an IP/full-chip using System Verilog/UVM. Expertise in PCIe/DDR verification is preferable at IP/chip level. Skills: Overall 3+ years industry experience in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC...