System Verification Engineer
1 week ago
his is what you are responsible for :
- Develop and maintain verification plans, testbenches, and test cases for ASIC designs.
- Collaborate with design and architecture teams to understand design specifications and requirements.
- Design and implement System Verilog/UVM-based verification environments.
- Create and execute test cases to verify functionality, performance, and compliance with specifications.
- Debug failures and drive issues to closure, working closely with cross-functional teams.
- Mentor junior team members and provide technical guidance.
- Contribute to the continuous improvement of verification methodologies and best practices.
- Create and maintain verification environments for SOCs.
Necessary Qualifications :
- 8 years of experience in ASIC verification, preferably in a senior or lead role.
- Strong expertise in SystemVerilog, UVM, OOP concepts and verification methodologies.
- Experience with verification tools such as VCS, QuestaSim, or similar.
- Proven track record of successfully delivering complex ASIC verification projects.
- Excellent problem-solving and debugging skills.
- Strong communication and teamwork abilities.
Preferred Qualifications :
- Experience with scripting languages such as Python or Perl.
- Knowledge of industry standards and protocols (e.g., PCIe, DDR, USB, Ethernet).
- Knowledge on the on chip interconnects, memory and processor subsystems.
- Familiarity with formal verification techniques.
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