
PMTS Silicon Design Engineer
3 weeks ago
- The ideal candidate is one, who has a proven track record on driving strategies and successful verification execution on Block level and System level verification of high-performance IPs and/or SOC designs.
Qualifications:
- Experience (15+ years) in Technically leading a team and working with cross-functional teams, planning inter-locks with dependent teams, pre-empting the risks and having a plan to mitigate.
- Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify high performance IPs and/or SOC designs.
- Proven track record on driving strategies and successful verification execution on high performance IPs and/or SOC designs.
- Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools, and infrastructure for high performance-IP and/or VLSI designs is a plus.
- Experience with FPGA programming and software is a plus.
- Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) are a plus.
- Experience with gate level simulation, power aware verification, reset verification, contention checking is a plus.
- Prior experience with silicon debug at the tester and board level, is a plus.
ACADEMIC CREDENTIALS:
- Bachelors orMastersdegree in computer engineering/Electrical Engineering
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