
15h Left Senior Design Verification Engineer
3 weeks ago
Experience : 5-6 years
Location : Bangalore & Hyderabad
Responsibilities:
a. Individual Contributor b. To understand the design spec, features, SoC requirements and verify the design accordingly. c. Owning 200 to 250 attributes/scenarios per project d. Ensure functional coverage , Code coverage is closed 100% within timelines e. Should be capable of integrating VIPs , creating new scenarios f. Capable of writing assertions Skill Requirements: a. SoC Level verification experience b. SV, Verilog, UVM methodology c. UVM RAL d. Scripting knowledge and experience e. Well versed with SV Assertions f. Good debug skills at SoC level g. Protocols : AXI, AHB, APB h. Xcelium, Indago usage, vmanager i. Gate Level Simulation & debug experience j. Perforce commandsÂ
Good to have: a. Clock Tree verification background at SoC level b. Python expertise
Interested,please drop your updated CV to janagaradha.n@acldigital.com
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