Apply Now: Senior Design Verification Engineer- Singapore

4 weeks ago

Hyderabad India BITSILICA Full time

Job Description Over 4 years of experience in digital IP verification, with advanced knowledge of ASIC/SOC design flow and modern verification methodologies. About the Role Proficient in Verilog, SystemVerilog, and UVM. Strong understanding of UVM concepts and SystemVerilog features (SVA, UVM Scoreboard). Responsibilities - Skilled in defining and developing UVM-based verification frameworks, testbenches, processes, and flows. - Exposure to high-speed protocols such as USB, PCIe, UFS, SATA, Ethernet (plus). - Knowledge of AMBA interconnects (AXI, APB, AHB) (plus). Qualifications - Over 4 years of experience in digital IP /SOC verification. Required Skills - Advanced knowledge of ASIC/SOC design flow. - Proficient in Verilog, SystemVerilog, and UVM. - Strong understanding of UVM concepts and SystemVerilog features (SVA, UVM Scoreboard). Preferred Skills - Exposure to high-speed protocols such as USB, PCIe, UFS, SATA, Ethernet. - Knowledge of AMBA interconnects (AXI, APB, AHB).

  • Senior Design Verification Engineer SIngapore

    4 weeks ago

    Hyderabad, India BITSILICA Full time

    Job Description Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: - Test bench development and debug - Strong Expertise in Digital, Verilog & SV. - UVM/C based test case development and debug. - Power aware test case development and debug - External/Internal VIP based test development and debug. - Mixed-signal...

  • Senior Design Verification Engineer SIngapore

    3 weeks ago

    Hyderabad, India BITSILICA Full time

    Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...

  • Senior Design Verification Engineer SIngapore

    2 weeks ago

    Hyderabad, India BITSILICA Full time

    Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...

  • Senior Design Verification Engineer SIngapore

    3 weeks ago

    Hyderabad, India BITSILICA Full time

    Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...

  • Senior Design Verification Engineer SIngapore

    2 hours ago

    Hyderabad, India BITSILICA Full time

    Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...

  • Senior Design Verification Engineer SIngapore

    3 weeks ago

    Hyderabad, Telangana, India, Telangana BITSILICA Full time

    Skill: Senior DV EngineerExp: 5-10 YearsLocation: SingaporeNotice: Immediate - 30 days JD:Test bench development and debugStrong Expertise in Digital, Verilog & SV.UVM/C based test case development and debug.Power aware test case development and debugExternal/Internal VIP based test development and debug.Mixed-signal block modelling and RNM based...

  • Senior Design Verification Engineer SIngapore

    1 week ago

    Hyderabad, Telangana, India BITSILICA Full time $ 1,50,000 - $ 2,00,000 per year

    Skill: Senior DV EngineerExp: 5-10 YearsLocation: SingaporeNotice: Immediate - 30 daysJD:Test bench development and debugStrong Expertise in Digital, Verilog & SV.UVM/C based test case development and debug.Power aware test case development and debugExternal/Internal VIP based test development and debug.Mixed-signal block modelling and RNM based...

  • Senior Design Verification Engineer

    2 days ago

    Hyderabad, Telangana, India Quest Global Full time ₹ 6,00,000 - ₹ 12,00,000 per year

    Job Requirements Job Title: Senior Design Verification Engineer We are currently seeking a skilled Design Verification Engineer to join our team. As a Design Verification Engineer, you will be responsible for verifying and validating complex digital designs to ensure they meet the required specifications and standards. Key Responsibilities: Develop and...

  • [Only 24h Left] Senior Design Verification Engineer SIngapore

    3 weeks ago

    Hyderabad, India BITSILICA Full time

    Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: - Test bench development and debug - Strong Expertise in Digital, Verilog & SV. - UVM/C based test case development and debug. - Power aware test case development and debug - External/Internal VIP based test development and debug. - Mixed-signal block modelling and...

  • Senior Design Verification Engineer

    1 week ago

    Hyderabad, India ACL Digital Full time

    Senior Design Verification Engineer - Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging. - Should be an enthusiastic and a quick learner of the verification flow. Job Description: - SV / UVM Test bench development and test cases coding - Code and Functional...