Senior Design Verification Engineer SIngapore

2 weeks ago

Hyderabad India BITSILICA Full time

Job Description Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: - Test bench development and debug - Strong Expertise in Digital, Verilog & SV. - UVM/C based test case development and debug. - Power aware test case development and debug - External/Internal VIP based test development and debug. - Mixed-signal block modelling and RNM based testing. - Coverage analysis (code, functional, assertion) - Verification plan reviews, Verification reviews - Back-annotated netlist simulation execution and debug - Debug failing cases & Coverage improvements.

  • Senior Design Verification Engineer SIngapore

    1 week ago

    Hyderabad, India BITSILICA Full time

    Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...

  • Senior Design Verification Engineer SIngapore

    1 week ago

    Hyderabad, India BITSILICA Full time

    Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...

  • Senior Design Verification Engineer SIngapore

    4 days ago

    Hyderabad, India BITSILICA Full time

    Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...

  • Senior Design Verification Engineer SIngapore

    1 week ago

    hyderabad, India BITSILICA Full time

    Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...

  • Senior Design Verification Engineer SIngapore

    2 weeks ago

    Hyderabad, Telangana, India, Telangana BITSILICA Full time

    Skill: Senior DV EngineerExp: 5-10 YearsLocation: SingaporeNotice: Immediate - 30 days JD:Test bench development and debugStrong Expertise in Digital, Verilog & SV.UVM/C based test case development and debug.Power aware test case development and debugExternal/Internal VIP based test development and debug.Mixed-signal block modelling and RNM based...

  • [Only 24h Left] Senior Design Verification Engineer SIngapore

    2 weeks ago

    Hyderabad, India BITSILICA Full time

    Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: - Test bench development and debug - Strong Expertise in Digital, Verilog & SV. - UVM/C based test case development and debug. - Power aware test case development and debug - External/Internal VIP based test development and debug. - Mixed-signal block modelling and...

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    3 weeks ago

    Bengaluru, India ARF Design Pvt Ltd Full time

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    Visakhapatnam, Andhra Pradesh, India, Andhra Pradesh Eximietas Design Full time

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  • Senior Design Verification Engineer SIngapore

    1 week ago

    Hyderabad, India BITSILICA Full time

    Skill: Senior DV EngineerExp: 5-10 YearsLocation: SingaporeNotice: Immediate - 30 daysJD:Test bench development and debugStrong Expertise in Digital, Verilog & SV.UVM/C based test case development and debug.Power aware test case development and debugExternal/Internal VIP based test development and debug.Mixed-signal block modelling and RNM based...

  • Senior Design Verification Engineer SIngapore

    1 week ago

    Hyderabad, India BITSILICA Full time

    Skill: Senior DV EngineerExp: 5-10 YearsLocation: SingaporeNotice: Immediate - 30 daysJD:Test bench development and debugStrong Expertise in Digital, Verilog & SV.UVM/C based test case development and debug.Power aware test case development and debugExternal/Internal VIP based test development and debug.Mixed-signal block modelling and RNM based...