Sr. RTL Design Engineer with Video protocols

Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

THE ROLE:

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

Job Description (JD):

We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of AMD-Xilinx FPGA Architecture. In this role, you will design Register-Transfer Level (RTL) Intellectual Property (IP) with a focus on video connectivity subsystems. You will have dynamic, multi-faceted responsibilities in areas such as project definition, RTL design, and implementation. You will participate in the design, architecture, documentation, and implementation of the low latency video connectivity systems. You will be also responsible for RTL coding of blocks specified by you or others. Additionally, you will be responsible for various front-end methodology flows that include resource optimization, clock domain crossing and reset domain crossing.

Qualifications:

- Must have proven experience working on Video domain IPs / Digital IPs.
- Must have proven experience working of one or more of protocols at the IP level: MIPI CSI / MIPI DSI / DisplayPort /HDMI / SDI.
- Hands on experience with AMD/Xilinx FPGA device and Vivado toolchain.
- Hands on experience with architecting / micro-architecture / detailed design from functional specifications.
- Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for FPGA designs.
- Lint, CDC, synthesis flow and static timing flows, formal checking, etc. experience.
- Working knowledge / experience TCL, Perl, Python is an added advantage.
- SERDES architecture knowledge is a plus.
- Has a solid desire to learn and explore new technologies.
- Strong communication and presentation skills.
- Close collaboration with different teams across various time zones.

ACADEMIC CREDENTIALS:

- Bachelor's or Master's degree in computer engineering/Electrical Engineering with 5+ years of exp

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Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.