Principal Engineer, Physical Design Timing

2 weeks ago


Bangalore Karnataka, India Intel Full time

Job Details In this role you will be responsible for Timing methodology definition and closure of designs using industry standard tools for chiplet designs for custom and domain specific products The chiplets will be leveraged to enable modular design and support multiple products As part of this team the candidate will work with leading edge technologies and solutions across multiple domains including SoC multi-die implementations 2 5 and 3D power delivery leading edge memory technologies innovate thermal solutions on die clocking and fabrics The team will also look at options to enhance product power performance area cost thru improved tools and methodologies The successful candidate would be expected to Responsibilities 1 Drive PV convergence signoff including static timing ERC checks ECO flows and power analysis 2 Defining clock frequencies PV guard-banding signoff PV corners ERC checks Clock Reset domain crossing design constraints 3 Develop and recommend design methodologies to enable more efficient and faster design convergence 4 Scripting in an interpreted language TCL py 5 Ability to work independently and at various levels of abstraction 6 Strong analytical ability and problem solving skills 7 Ability to work effectively with both internal and external teams customers is expected 8 Strong written and verbal communication skills 9 Ability to mentor other engineers and technically guide them Job posting details such as work model location or time type are subject to change Qualifications Minimum Qualifications 1 Bachelor Master degree in CS CE or EE or equivalent experience 2 10 years of Physical design experience with a strong understanding of digital circuits and proficiency in static timing analysis STA tools like PrimeTime or Innovus 3 Experience with signoff corner selection PV guard-banding PV convergence including static timing and power analysis 4 Strong experience in SoC and ASIC design flows on taped out designs 5 Expertise in timing closure at block chip level and ECO flows 6 Experience with scripting in an interpreted languagePreferred Qualifications 1 Experience with full chip integration die-to-die and package integration level timing signoff2 Hands-on experience with synthesis block and chip level implementation with industry standard PnR flows and tools3 Strong experience in CPU and GPU design flows on taped out designs 4 Design tools and methods development5 Capable of working in a high performing team to deliver the results required from the organization Job Type Experienced HireShift Shift 1 India Primary Location India BangaloreAdditional Locations India HyderabadBusiness group The Data Center Artificial Intelligence Group DCAI is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart connected computing devices The data center is the underpinning for every data-driven service from artificial intelligence to 5G to high-performance computing and DCG delivers the products and technologiesxe2x80x94spanning software processors storage I O and networking solutionsxe2x80x94that fuel cloud communications enterprise and government data centers around the world Posting Statement All qualified applicants will receive consideration for employment without regard to race color religion religious creed sex national origin ancestry age physical or mental disability medical condition genetic information military and veteran status marital status pregnancy gender gender expression gender identity sexual orientation or any other characteristic protected by local law regulation or ordinance Position of Trust This role is a Position of Trust Should you accept this position you must consent to and pass an extended Background Investigation which includes subject to country law extended education SEC sanctions and additional criminal and civil checks For internals this investigation may or may not be completed prior to starting the position For additional questions please contact your Recruiter Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site Job posting details such as work model location or time type are subject to change



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